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PDF SST39VF3201B Data sheet ( Hoja de datos )
| Número de pieza | SST39VF3201B | |
| Descripción | (SST39VF3201B / SST39VF3202B) 32 Mbit (x16) Multi-Purpose Flash Plus | |
| Fabricantes | SST | |
| Logotipo |  |
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32 Mbit (x16) Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
FEATURES:
SST39VF640xB2.7V 64Mb (x16) MPF+ memories
Data Sheet
• Organized as 2M x16
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Superior Reliability
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 6 mA (typical)
– Standby Current: 4 µA (typical)
– Auto Low Power Mode: 4 µA (typical)
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 32 KWord)
for SST39VF3202B
– Bottom Block-Protection (bottom 32 KWord)
for SST39VF3201B
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Security-ID Feature
– SST: 128 bits; User: 128 words
• Fast Read Access Time:
– 70 ns
• Latched Address and Data
• Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 35 ms (typical)
– Word-Program Time: 7 µs (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pin Assignments
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST39VF320xB devices are 2M x16 CMOS Multi-
Purpose Flash Plus (MPF+) manufactured with SST’s pro-
prietary, high-performance CMOS SuperFlash technology.
The split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST39VF320xB write (Pro-
gram or Erase) with a 2.7-3.6V power supply. These
devices conform to JEDEC standard pin assignments for
x16 memories.
Featuring high performance Word-Program, the
SST39VF320xB devices provide a typical Word-Program
time of 7 µsec. These devices use Toggle Bit or Data# Poll-
ing to indicate the completion of Program operation. To pro-
tect against inadvertent write, they have on-chip hardware
and Software Data Protection schemes. Designed, manu-
factured, and tested for a wide spectrum of applications,
these devices are offered with a guaranteed typical endur-
ance of 100,000 cycles. Data retention is rated at greater
than 100 years.
The SST39VF320xB devices are suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applications,
©2009 Silicon Storage Technology, Inc.
S71384-01-000
1/09
1
they significantly improve performance and reliability, while
lowering power consumption. They inherently use less
energy during Erase and Program than alternative flash
technologies. The total energy consumed is a function of
the applied voltage, current, and time of application. Since
for any given voltage range, the SuperFlash technology
uses less current to program and has a shorter erase time,
the total energy consumed during any Erase or Program
operation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high-density, surface mount requirements, the
SST39VF320xB devices are offered in 48-lead TSOP and
48-ball TFBGA packages. See Figure 2 and Figure 3 for
pin assignments.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Free Datasheet http://www.datasheet4u.com/
1 page  
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Product Identification
The Product Identification mode identifies the devices as
the SST39VF3201B and SST39VF3202B, and the manu-
facturer as SST. This mode may be accessed through
software operations. Users may use the Software Product
Identification operation to identify the part (i.e., using the
device ID) when using multiple manufacturers in the same
socket. For details, see Table 6 for software operation,
Figure 13 for the Software ID Entry and Read timing dia-
gram and Figure 23 for the Software ID Entry command
sequence flowchart.
TABLE 3: Product Identification
Manufacturer’s ID
Device ID
SST39VF3201B
SST39VF3202B
Address
0000H
0001H
0001H
Data
BFH
235DH
235CH
T3.0 1384
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 6 for software command
codes, Figure 15 for timing waveform, and Figure 23 and
Figure 24 for flowcharts.
Data Sheet
Security ID
The SST39VF320xB devices offer a 136 word Security ID
space. The Secure ID space is divided into two segments -
one factory programmed segment and one user pro-
grammed segment. The first segment is programmed and
locked at SST with a random 128-bit number. The 128-
word user segment is left un-programmed for the customer
to program as desired.
To program the user segment of the Security ID, the user
must use the Security ID Word-Program command. To
detect end-of-write for the SEC ID, read the toggle bits. Do
not use Data# Polling. Once this is complete, the Sec ID
should be locked using the User Sec ID Program Lock-Out.
This disables any future corruption of this space. Note that
regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.
The Secure ID space can be queried by executing a three-
byte command sequence with Enter Sec ID command
(88H) at address 555H in the last byte sequence. To exit
this mode, the Exit Sec ID command should be executed.
Refer to Table 6 for more details.
©2009 Silicon Storage Technology, Inc.
5
S71384-01-000
1/09
Free Datasheet http://www.datasheet4u.com/
5 Page 
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
Operating Range
Range
Commercial
Industrial
Ambient Temp
0°C to +70°C
-40°C to +85°C
VDD
2.7-3.6V
2.7-3.6V
AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 19 and 20
Power Up Specifications
All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100 ms (0V to 3V
in less than 300 ms). If the VDD ramp rate is slower than 1V per 100 ms, a hardware reset is required. The recom-
mended VDD power-up to RESET# high time should be greater than 100 µs to ensure a proper reset.
VDD
RESET#
CE#
FIGURE 4: Power-Up Diagram
TPU-READ > 100 µs
VDD min
0V
VIH
TRHR > 50ns
1384 F24.0
©2009 Silicon Storage Technology, Inc.
11
S71384-01-000
1/09
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet SST39VF3201B.PDF ] | |
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