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PDF AK5730 Data sheet ( Hoja de datos )
| Número de pieza | AK5730 | |
| Descripción | 4-Channel Differential Audio ADC | |
| Fabricantes | AKM | |
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[AK5730]
AK5730
4-Channel Differential Audio ADC for Line & Mic Inputs
GENERAL DESCRIPTION
The AK5730 features a 4-channel Differential ADC with SAR ADC for DC measurement. Differential ADC
supports Line and Microphone-input, making it ideal for microphone array applications. TDM audio format
makes it easy to connect with DSP.
FEATURES
1. Audio ADC
- 4-Channel Audio ADC
- Full-differential Input
- Input Voltage:
Mic: 1.65Vrms,
LINE and Phone: 3Vrms(with external resistors) programmable
Boost input: 11.7Vrms(with external resistors) programmable
- ADC Performance:
S/(N+D): typ 92dB
DR, S/N: typ 100dB
- Digital HPF for DC-offset cancellation: fc=1Hz with individual on/off
2. SAR ADC
- 1ch SAR ADC with 9:1 MUX
- Reference Voltage: Ground
3. Sampling Rate: 8kHz ~ 48kHz
4. Master Clock: 256fs, 384fs, 512fs or Internal PLL
5. Master/Slave mode
6. Audio Interface Format: MSB First, 2’s complement
- 24bit I2S
- 24bit TDM interface up to 4 ICs cascade
7. Channel Independent Microphone Diagnostics
- open microphone
- shorts to battery
- shorts to ground
- shorts across inputs
- microphone bias over current
- over temperature
8. Programmable Microphone Bias: 5V to 9V with 0.5V step
9. μP I/F: I2C Bus (Ver 1.0, 400kHz Mode) or SPI
10. Power Supply:
VDD: 3.0 ∼ 3.6V
11. Ta = −40 ∼ 105°C
12. Package: 48pin LQFP
Rev 0.8
-1-
2013/06
Free Datasheet http://www.datasheet4u.com/
1 page  
[AK5730]
No. Pin Name
28 CN2
29 NC
30 VSS2
31 DVDD
32 CN1
33 CP1
34 CVP1
35 NC
36 MPWR
I/O Function
Negative Charge Pump Capacitor Terminal Pin 2
Connect to CP2 with a 2.2μF capacitor that should have the low ESR (Equivalent Series
Resistance) over all temperature range. When this capacitor has the polarity, the positive
I
polarity pin should be connected to the CP2 pin. Non polarity capacitors can also be
used.
* The maximum bias voltage of this pin is 7.2V. The capacitance variation of an external
capacitor should be in the range of 2.2μF +20% and -40% including the difference by a
tolerance, a rate of temperature change and a bias voltage.
- This pin should be connected to VSS1.
- Digital Ground Pin and Charge Pump Ground Pin , 0V
Digital Power Supply Pin and Charge Pump Circuit Positive Power Supply Pin 3.0V∼3.6V
- Normally connected to VSS2 with a 0.1μF ceramic capacitor in parallel with a 10μF
electrolytic cap.
Positive Charge Pump Capacitor Terminal Pin 1
Connect to CN1 with a 2.2μF capacitor that should have the low ESR (Equivalent Series
Resistance) over all temperature range. When this capacitor has the polarity, the positive
I
polarity pin should be connected to the CN1 pin. Non polarity capacitors can also be
used.
* The maximum bias voltage of this pin is 3.6V. The capacitance variation of an external
capacitor should be in the range of 2.2μF +20% and -40% including the difference by a
tolerance, a rate of temperature change and a bias voltage.
Negative Charge Pump Capacitor Terminal Pin 1
Connect to CP1 with a 2.2μF capacitor that should have the low ESR (Equivalent Series
Resistance) over all temperature range. When this capacitor has the polarity, the positive
I
polarity pin should be connected to the CP1 pin. Non polarity capacitors can also be
used.
* The maximum bias voltage of this pin is 3.6V. The capacitance variation of an external
capacitor should be in the range of 2.2μF +20% and -40% including the difference by a
tolerance, a rate of temperature change and a bias voltage.
Charge Pump Circuit Positive Voltage Output Pin 1
Connect to VSS2 with a 2.2μF capacitor that should have the low ESR (Equivalent Series
Resistance) over all temperature range. When this capacitor has the polarity, the positive
O
polarity pin should be connected to the VSS2 pin. Non polarity capacitors can also be
used.
* The maximum bias voltage of this pin is 7.2V. The capacitance variation of an external
capacitor should be in the range of 2.2μF +20% and -40% including the difference by a
tolerance, a rate of temperature change and a bias voltage.
- This pin should be connected to VSS1.
MIC Power Supply Pin
Normally connected to VSS1 with a 1μF ceramic capacitor.
O * The maximum bias voltage of this pin is 10V. The capacitance variation of an external
capacitor should be in the range of 1μF +20% and -40% including the difference by a
tolerance, a rate of temperature change and a bias voltage.
Rev 0.8
-5-
2013/06
Free Datasheet http://www.datasheet4u.com/
5 Page 
[AK5730]
SWITCHING CHARACTERISTICS
(Ta=-40∼+105°C; AVDD=DVDD=3.0∼3.6V; CL=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
Master Clock Timing
External Clock
256fs:
fCLK
2.048
Pulse Width Low
tCLKL
32
Pulse Width High
tCLKH
32
384fs:
fCLK
3.072
Pulse Width Low
tCLKL
22
Pulse Width High
tCLKH
22
512fs:
fCLK
4.096
Pulse Width Low
tCLKL
16
Pulse Width High
tCLKH
16
LRCK Timing (Slave mode)
Stereo mode
(TDM1/0 bit = “00”)
frequency
fs 8
Duty Cycle
Duty
45
TDM256 mode
(Note 16)
(TDM1/0 bit = “01”)
LRCK frequency
fsn 8
“H” time
tLRH
1/256fs
“L” time
tLRL
1/256fs
TDM512 mode
(Note 16)
(TDM1/0 bit = “10”)
LRCK frequency
fsn 8
“H” time
tLRH
1/512fs
“L” time
tLRL
1/512fs
LRCK Timing (Master Mode)
Stereo mode
(TDM1/0 bit = “00”)
Normal Speed Mode
fsn 8
Duty Cycle
Duty
-
TDM256 mode
(Note 16)
(TDM1/0 bit = “01”)
LRCK frequency
fsn 8
“H” time
(Note 17) tLRH
TDM512 mode
(Note 16)
(TDM1/0 bit = “10”)
LRCK frequency
fsn 8
“H” time
(Note 17) tLRH
Note 16. Master clock should be input the 256fs/512fs in Master mode.
Note 17. If the format is I2S, it is “L” time.
50
1/8fs
1/16fs
max
12.288
18.432
24.576
48
55
48
48
48
-
48
48
Unit
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
kHz
%
kHz
ns
ns
kHz
ns
ns
kHz
%
kHz
ns
kHz
ns
Rev 0.8
- 11 -
2013/06
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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