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ANX7150 데이터시트 PDF




Analogix에서 제조한 전자 부품 ANX7150은 전자 산업 및 응용 분야에서
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부품번호 ANX7150 기능
기능 Zero Power HDMI 1.3 Transmitter
제조업체 Analogix
로고 Analogix 로고


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ANX7150 데이터시트, 핀배열, 회로
Preliminary
ANX7150
Zero Power HDMI® 1.3 Transmitter
HDMI 1.3 compatible transmitter with patented
Zero power HDMI transmitter technology
Optional HDCP function with internal keys
Supports link date rates up to 165Mpixel/sec
Flexible video pixel input interface, supports
DVD and HD MPEG decoders
- 24-bit RGB/YCbCr 4:4:4
- 16/20/24-bit YCbCr 4:2:2
- 8/10/12-bit YC Mux(ITU 601 and 656)
A CoolHD™ family product
Backward compatible with DVI1.1
Programmable output swing
6KV ESD performance
RoHS compliant and Halogen free package
Package offered
- 48-pin QFN
- 80-pin LQFP
- 81-pin VFBGA
- 81-pin TFBGA
- YCbCr-to-RGB colour space conversion
- YCbCr 4:2:2 to 4:4:4 up-sample
- 12-bit, dual-edge clocking input mode
- 8-bit DDR YCMux (ITU 601 and 656)
Advanced digital audio interface
- 8-channel I2S support Dolby Digital and
DVD-Audio
- Up to 6 channels 1-bit super audio support
- S/PDIF supports PCM, Dolby Digital and DTS
digital audio transmission
- IEC 60958 or 61937 compatible
- 2:1 and 4:1 down-sample to handle 96 KHz and
192 KHz audio stream
ANX7150, a CoolHDfamily product, it is a
revolutionary breakthrough technology that makes a
zero power HDMI transmitter a reality. CoolHD
technology solves the problem by recovering power
from the HDMI link that is normally wasted as heat
and using it to power the HDMI transmitter. This
technology is transforming the mobile and handheld
markets.
ANX7150 can be ordered with an optional HDCP 1.2
function (including internal keys) to support content
protection.
Built-in video pattern generator and audio tone
generator are included for system self-test.
Power requirement is 1.8V and 3.3V.
Software-controlled power management
For package and HDCP options, refer to the parts
ordering information.
DATA_CLK
D
VSYNC
HSYNC
DE
SCK/SAUD_CLK
SDO/SAUD0
SD1/SAUD1
SD2/SAUD2
SD3/SAUD3
WS/SAUD4
MCLK
SPDIF/SAUD5
CSDA
CSCL
INTP
PLL
Video Data Capture
DE Gen BIST
4:2:2 to 4:4:4
YCbCr to RGB
Audio Data Capture
BIST
I2C
Slave
Auxiliary
Packet Gen
HDCP Key
ROM
HDCP
Authorization
& Encryption
Configuration
Registers
DDC Bridge
Optional HDCP
Function
TMDS
Tx
DDC
Master
TX0_P/N
TX1_P/N
TX2_P/N
TXC_P/N
R_BIAS
HPD
DSCL
DSDA
ANX7150 Block Diagram
Free Datasheet http://www.datasheet4u.com/




ANX7150 pdf, 반도체, 판매, 대치품
Preliminary
ANX7150
DVSS
DVSS
DVDD18
SPDIF/SAUD5
GPIO
VOREGC
TXCN
TXCP
AVSS
AVSS
TX0N
TX0P
VOREG0
VOREG1
TX1N
TX1P
AVSS
TX2N
TX2P
VOREG2
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
ANX7150
80-Pin LQFP
(Top View)
40 D[18]
39 D[17]
38 D[16]
37 D[15]
36 D[14]
35 DVDD18
34 DVSS
33 DVSS
32 DVDD33
31 D[13]
30 D[12]
29 D[11]
28 D[10]
27 D[9]
26 D[8]
25 DE
24 HSYNC
23 VSYNC
22 DVSS
21 DVDD18
Figure 2-2 ANX7150 80-pin LQFP
Rev 1.3
Analogix Confidential
Page 4 of 33
Free Datasheet http://www.datasheet4u.com/

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ANX7150 전자부품, 판매, 대치품
Preliminary
ANX7150
2.1Pin Definition
2.1.1 Video Interface Pins
Table 2-1 Video Interface Pins
81-pin VFBGA/TFBGA 80-pin
E2 10
48-pin
10
Name
DATA_CLK
J3 25 15 DE
J2 23 13 VSYNC
H3 24 14 HSYNC
F1,F2,G1,G2,G3,H1,
H2,J1,J4,H4,J5,H5,
G5,J6,H6,J7,H7,J8,
H8,J9,H9,G9,G8,G7
13-20,
26-31,
36-45
11,12,
16-21
D
I/O Type
I LVTTL
I LVTTL
I LVTTL
I LVTTL
I LVTTL
Description
Pixel clock input. 25 MHz ~ 165 MHz.
Data enable.
Vertical sync. Input control signal.
Horizontal sync. Input control signal.
Pixel data input.
2.1.2 Audio Interface Pins
Table 2-2 Audio Interface Pins
81-pin
80-pin 48-pin
VFBGA/TFBGA
C5 64 NC
Name
SPDIF/SAUD5
I/ Type
O
I LVTTL
D8
55 31 MCLK
I LVTTL
F7 46 25 SCK/SAUD_CLK I LVTTL
D9
54 30 WS/SAUD4
I LVTTL
E9
53
NC
SD3/SAUD3
I LVTTL
E8
52
NC
SD2/SAUD2
I LVTTL
F9
49
NC
SD1/SAUD1
I LVTTL
F8
48 27
SD0/SAUD0
I LVTTL
SD0/SPDIF
Description
S/PDIF audio input or super audio input
channel 5.
Audio master clock input.
I2S audio clock or super audio clock input.
I2S audio word select or super audio input
channel 4.
8-channel I2S audio data input or super audio
input channel 03.
For 48-pin QFN device, it is S/PDIF audio
input.
2.1.3 I2C Interface Pins
Table 2-3 I2C Interface Pins
81-pin VFBGA/TFBGA 80-pin
C2 5
48-pin
5
Name
SSCL
D2 6 6 SSDA
C9 57 33 DSCL
C8 56 32 DSDA
B6 60 36 TEST_EN
I/O Type
I LVTTL
I/O LVTTL
O LVTTL
I/O LVTTL
I/O LVTTL
Description
Slave I2C clock input.
Slave I2C data. Open drain output.
DDC (Master I2C) clock output.
DDC (Master I2C) data. (open drain
output).
Scan test enable
2.1.4 Serial Interface Pins
Table 2-4 Serial Interface Pins
81-pin VFBGA/TFBGA 80-pin
A5,A6
71,72
48-pin
40,41
Name
TX0N/P
A2,A3
75,76 44,45 TX1N/P
B1,C1
78,79 46,47 TX2N/P
I/O Type
O TMDS
O TMDS
O TMDS
Description
Channel 0 TMDS differential output.
Channel 1 TMDS differential output.
Channel 2 TMDS differential output.
Page 7 of 33
Analogix Confidential
Rev 1.3
Free Datasheet http://www.datasheet4u.com/

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