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64F7058 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 64F7058
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64F7058 데이터시트, 핀배열, 회로
REJ09B0046-0300H
The revision list can be viewed directly by
clicking the title page.
The rivision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
32
SH-2E SH7058 F-ZTAT TM
Hardware Manual
Renesas SuperHTM RISC engine
Rev. 3.00
Revision date: Sep. 17, 2004
www.renesas.com
Free Datasheet http://www.datasheet4u.com/




64F7058 pdf, 반도체, 판매, 대치품
Preface
The SH7058 is a single-chip RISC (reduced instruction set computer) microcomputer that has the
32-bit internal architecture CPU, SH-2E, as its core, and also includes peripheral functions
necessary for system configuration.
The SH7058 is equipped with on-chip peripheral functions necessary for system configuration,
including a floating-point unit (FPU), large-capacity ROM and RAM, a direct memory access
controller (DMAC), timers, a serial communication interface (SCI), controller area network
(HCAN), A/D converter, and I/O ports, therefore, it can be used as a microprocessor built in a
high-level control system.
The SH7058 is an F-ZTAT™* (Flexible Zero Turn-Around Time) version with flash memory as
its on-chip ROM, and it can rapidly and flexibly deal with each situation on an application system
with fluid specifications from an early stage of mass production to full-scale production.
Note: * F-ZTAT™ is a trademark of Renesas Technology, Corp.
Target users: This manual was written for users who will be using the SH7058 F-ZTAT in the
design of application systems. Users of this manual are expected to understand
the fundamentals of electrical curcuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the SH7058 F-ZTAT to the above users.
Refer to the SH-2E Programming Manual for a detailed description of the
instruction set.
Notes on reading this manual:
In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
In order to understand the details of the CPU's functions
Read the SH-2E Programming Manual.
Rule:
Bit order: The MSB (most significant bit) is on the left and the LSB (least
significant bit) is on the right.
Releated Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
Rev. 3.0, 09/04, page i of xxxviii
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64F7058 전자부품, 판매, 대치품
Item
7.5 Interrupt Response Time
Table 7.5 Interrupt Response Time
7.5 Interrupt Response Time
Figure 7.4 Example of Pipeline
Operation when an IRQ Interrupt is
Accepted
Page Revisions (See Manual for Details)
122
123
Table amended
Item
Number of States
Peripheral
Module
NMI
IRQ
Notes
Synchronizing input signal
(synchronized with
peripheral clock Pφ) with
internal clock φ and DMAC
activation judgment
0 or 6
[0 or 3]
Compare identified interrupt 2
priority with SR mask level
1 to 4
[1 or 2]
2
6 to 9
[3 to 5]
2
For the number of states
required for each interrupt,
see the note (*) below.
The values enclosed in [ ]
are values for when the
multiplication ratio is 4.
Wait for completion of
sequence currently
being executed by CPU
X (0)
Time from start of interrupt
exception processing until
fetch of first instruction of
exception service routine
starts
Interrupt
response time
Total:
Minimum:
5 + m1 + m2 + m3
(7 or 13) +
m1 + m2 +
m3 + X
10
(8 to 11) +
m1 + m2 +
m3 + X
11
The longest sequence is for
interrupt or address-error
exception processing (X = 4
+ m1 + m2 + m3 + m4). If an
interrupt-masking instruction
follows, however, the time
may be even longer.
Performs the PC and SR
saves and vector address
fetch.
(13 to 16) +
m1 + m2 +
m3 + X
16
Maximum: 17 + 2 (m1 + 15 + 2 (m1 + 20 + 2 (m1 +
m2 + m3) + m2 + m3) + m2 + m3) +
m4 m4 m4
Note: * Number of states needed for synchronization and DMAC activation judgment
The relations between numbers of states needed for synchronizing an input signal
(synchronized with the peripheral clock Pφ) with the internal clock φ and DMAC activation
judgment and vector numbers are shown below.
0 state: 9, 10, 12, 13, 14, 72, 74, 76, 78, 189, 193, and 224
6 states: Peripheral module interrupts other than the above. However, vector number
222 (HCAN0/RM0) is different from the others.
For an interrupt with vector number 222 (HCAN0/RM0), the needed states differ from
other interrupts since the interrupt by HCAN0 mailbox 0 can activate the DMAC.
HCAN0 mailbox 0: 7 states
Other than above: 6 states
The same number of states is needed to cancel interrupt sources.
If the necessary number of states is not secured after flag clear of the interrupt
source, the interrupt may occur again.
Figure amended
IRQ
Synchronization
of IRQ
Interrupt controller
processing
Interrupt acceptance
6 to 9
5 + m1 + m2 + m3
2 3 m1 m2 1 m3 1
Instruction
F D E EMM EM E E
Overrun fetch
Interrupt service routine
start instruction
F
FDE
9.1.5 Address Map
146
Table 9.3 Address Map
Number of Access Cycles for On-Chip
Peripheral Module Registers
10.3.2 DMA Transfer Requests
179
Newly added
Description added
In on-chip peripheral module request mode, when the
DMAC accepts the transfer request, the next transfer
request is ignored until a single transfer ends in cycle
steal mode or all transfers end in burst mode. Only
when the address reload function is used, the next
transfer request is accepted after the fourth transfer.
Rev. 3.0, 09/04, page iv of xxxviii
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