PDF SI3226 Data sheet ( Hoja de datos )

Número de pieza	SI3226
Descripción	(SI3208 - SI3227) DUAL PROSLIC
Fabricantes	Silicon Laboratories
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Si3226/7 Si3208/9 DUAL PROSLIC® WITH DC-DC CONTROLLER Features Performs all BORSCHT functions Ideal for short- or long-loop applications Internal balanced or unbalanced ringing Low power consumption Software-programmable parameters: Ringing frequency, amplitude, cadence, and waveshape Two-wire ac impedance Transhybrid balance DC current loop feed (10–45 mA) Loop closure and ring trip thresholds Ground key detect threshold Integrated dc-dc controller Wideband CODEC (Si3227) Applications Low-power sleep mode On-hook transmission Loop or ground start operation Smooth polarity reversal DTMF generator/decoder A-Law/µ-Law companding, linear PCM PCM and SPI bus digital interfaces with programmable interrupts GCI/IOM-2 mode support 3.3 V operation GR-909 loop diagnostics Audio diagnostics with loopback Pb-free/RoHS-compliant packaging Customer Premises Equipment (CPE) Optical Network Terminals (ONT) Private Branch Exchange (PBX) Cable EMTAs, ATAs, VoIP Gateways Description The Dual ProSLIC® is a family of low-voltage CMOS devices that integrate both SLIC and CODEC functionality into a single IC. In combination with a linefeed IC (LFIC), they provide a complete two-channel analog telephone interface in accordance with all relevant LSSGR, ITU, and ETSI specifications. The Dual ProSLIC devices (Si3226/7) operate from a single 3.3 V supply and interface to standard PCM/SPI or GCI bus digital interfaces. The LFICs (Si3208/9) perform all high-voltage functions and operate from a 3.3 V supply as well as high-voltage battery supplies. The Si3208 is rated for –110 V, and the Si3209 is rated for – 135 V. The Dual ProSLIC devices are available in a 64-pin thin quad flat package (TQFP), and the LFICs are available in a 40-pin, quad flat no-lead package (QFN). Functional Block Diagram FSYNC DRX DTX CS SDI SDO SCLK INT RST PCLK Si3226/7 Si32068/9 PCM/ GCI Interface DTMF & Tone Gen Caller ID SPI Control Interface Ringing Generator DSP Line Diagnostics CODEC ADC SLIC Linefeed Control DAC Linefeed Monitor CODEC ADC SLIC Linefeed Control PLL DDCC--DDCCCCoonnttrroollleerrs DAC Linefeed Monitor TIP Channel 1 RING TIP Channel 2 RING VDC DC-DC BOM VBAT Ordering Information See page 33. Patents pending Preliminary Rev. 0.33 6/07 Copyright © 2007 by Silicon Laboratories Si3226/7 Si3208/9 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Free Datasheet http://www.datasheet4u.com/ 1 page Si3226/7 Si3208/9 Table 2. Recommended Operating Conditions Parameter Symbol Test Min* Typ Max* Unit Condition Ambient Temperature Ambient Temperature Supply Voltage, Si3226/7 Supply Voltage, Si3208/Si3209 Battery Voltage, Si3208 Battery Voltage, Si3209 TA TA VDD1–VDD4 VDD VBAT VBAT F-grade G-grade 0 –40 3.13 3.13 –9 –9 25 70 oC 25 85 oC 3.3 3.47 V 3.3 3.47 V — –110 V — –135 V *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. Table 3. 3.3 V Power Supply Characteristics1 (VDD = 3.3 V, TA = 0 to 70 ºC for F-Grade, –40 to 85 ºC for G-Grade) Parameter Symbol Test Condition Min Typ Max Unit High Impedance, Reset IDD IVBAT VT and VR = Hi-Z RST = 0 — 2.4 — mA — 0 — mA High Impedance, Open Current IDD IVBAT VT and VR = Hi-Z — 9.7 — mA — 0.6 — mA Forward/Reverse Sleep, On-hook Current IDD IVBAT VTR = –48 V — 15 — mA — 1.2 — mA Forward/Reverse Active, On-hook Current IDD IVBAT VTR = –48 V — 24 — mA — 1.2 — mA Forward/Reverse Active, Off-hook Current IDD IVBAT ILOOP = 30 mA RLOAD = 50 Ω — 43 — — 3.1 + ILOOP — mA mA Forward/Reverse OHT, On-hook Current IDD IVBAT VTR = –48 V — 43 — mA — 1.6 — mA Tip/Ring Open, On-hook Current IDD IVBAT VT or VR = –48 V VR or VT = Hi-Z — 23 — mA — 0.6 — mA Ringing Current IDD IVBAT VTR = 55 VRMS + 0 VDC balanced, sinusoidal, f = 20 Hz RLOAD = 5 REN = 1400 Ω — — 26 2.3 + IAVE — — mA mA Notes: 1. All specifications are for a single channel of Si3226/7 using Si3208/9 linefeed IC and based on measurements with all channels in the same operating state. 2. ILOOP is the dc current in the subscriber loop during the off-hook state. 3. IAVE is the average of the full-wave rectified current in the subscriber loop during ringing (IAVE = IPEAK x 2/π). Preliminary Rev. 0.33 5 Free Datasheet http://www.datasheet4u.com/ 5 Page Si3226/7 Si3208/9 Table 10. Switching Characteristics—SPI (VDDA = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL = 20 pF) Parameter Symbol Test Conditions Min Typ Max Cycle Time SCLK Rise Time, SCLK Fall Time, SCLK tc tr tf 62 — — — — 25 — — 25 Delay Time, SCLK Fall to SDO Active td1 — — 20 Delay Time, SCLK Fall to SDO Transition td2 — — 20 Delay Time, CS Rise to SDO Tri-state td3 — — 20 Setup Time, CS to SCLK Fall tsu1 25 — — Hold Time, CS to SCLK Rise th1 20 — — Setup Time, SDI to SCLK Rise Hold Time, SDI to SCLK Rise tsu2 th2 25 — — 20 — — Delay Time between Chip Selects tcs 220 — — SDI to SDITHRU Propagation Delay td4 — 4 10 Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDD –0.4 V, VIL = 0.4 V Unit ns ns ns ns ns ns ns ns ns ns ns ns SCLK CS SDI SDO SDITHRU tr tc tsu1 tsu2 th2 td1 td2 td4 Figure 1. SPI Timing Diagram tf th1 tcs td3 Preliminary Rev. 0.33 11 Free Datasheet http://www.datasheet4u.com/ 11 Page

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