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PDF SI3401 Data sheet ( Hoja de datos )
| Número de pieza | SI3401 | |
| Descripción | (SI3400 / SI3401) FULLY-INTEGRATED 802.3-COMPLIANT PD INTERFACE AND SWITCHING REGULATOR | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si3400
Si3401
FULLY-INTEGRATED 802.3-COMPLIANT PD INTERFACE
AND SWITCHING REGULATOR
Features
IEEE 802.3 standard-compliant
solution, including pre-standard
(legacy) PoE support
Highly-integrated IC enables
compact solution footprints
Minimal external components
Integrated diode bridges and
transient surge suppressor
Integrated switching regulator
controller with on-chip power
FET
Integrated dual current-limited
hotswap switch
Applications
Support non-isolated and
isolated switching topologies
Comprehensive protection
circuitry
Transient overvoltage
protection
Undervoltage lockout
Early power-loss indicator
Thermal shutdown protection
Foldback current limiting
Programmable classification
circuit
Low-profile 5 x 5 mm 20-pin QFN
Pb-Free and RoHS-compliant
Ordering Information:
See Ordering Guide on page
page 17.
Pin Assignments
5 x 5 mm QFN
(Top View)
Voice over IP telephones and
adapters
Wireless access points
Security cameras
Description
Point-of-sale terminals
Internet appliances
Network devices
High power applications (Si3401)
The Si3400 and Si3401 integrate all power management and control
functions required in a Power-over-Ethernet (PoE) powered device (PD)
application. The Si3400 and Si3401 convert the high voltage supplied over
the 10/100/1000BASE-T Ethernet connection into a regulated, low-voltage
output supply. The optimized architectures of the Si3400 and Si3401
minimize the solution footprint, reduce external BOM cost, and enable the
use of low-cost external components while maintaining high performance.
The Si3400 and Si3401 integrate the required diode bridges and transient
surge suppressors, thus enabling direct connection of ICs to the Ethernet
RJ-45 connector. The switching power FET and all associated functions are
also integrated. The integrated switching regulator supports isolated
(flyback) and non-isolated (buck) converter topologies. The Si3400 and
Si3401 support IEEE STD™ 802.3-2005 (future instances are referred to as
802.3) compliant solutions as well as pre-standard products, all in a single
IC. Standard external resistors connected to the Si3400 and Si3401 provide
the proper 802.3 signatures for the detection function and programming of
the classification mode. Startup circuits ensure well-controlled initial
operation of both the hotswap switch and the voltage regulator. The Si3400
and Si3401 are available in low-profile, 20-pin, 5 x 5 mm QFN packages.
While the Si3400 is designed for applications up to 10 W, the Si3401 is
optimized for higher power applications (up to approximately 15 W). See
also “AN313: Using the Si3400/01 in High Power Applications” for more
information.
20 19 18 17 16 15
EROUT 1
SSFT 2
VDD 3
ISOSSFT2 4
VNEG
(PAD)
14 CT1
13 CT2
12 VPOSF
11 SP1
5 6 7 8 9 10
Notes:
1. Pin VSSA added on revisions CZ
and higher.
2. Pin ISOSSFT added on revisions
CZ and higher. Function available
on revision E silicon. For Rev CZ,
or to disable this feature on
Revision E, tie this pin to VDD.
Rev. 0.9 8/07
Copyright © 2007 by Silicon Laboratories
Si3400/Si3401
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Free Datasheet http://www.datasheet4u.com/
1 page  
Si3400/Si3401
Table 2. Absolute Maximum Ratings (Transient)1
Transient surge defined in IEC60060 as a 1000 V impulse of either polarity applied across CT1–CT2 or SP1–SP2. The shape of
the impulse shall have a 300 ns full rise time and a 50 µs half fall time, with 201 Ω source impedance.
Type
Description
Rating
Unit
Voltage
CT1 to CT2
–82 to 82
SP1 to SP2
VPOS2
–82 to 82
–0.7 to 80
HSO
VSS1, VSS2, or VSSA
–0.7 to 80
–0.7 to 80
V
SWO
PLOSS to VPOS2
–0.7 to 80
–80 to 0.7
RDET
–0.7 to 80
Current
ESD3
CT1, CT2, SP1, SP2
VPOS2
HBM, all pins
–5 to 5
–5 to 5
–2 to 2
A
kV
Notes:
1. Unless otherwise noted, all voltages referenced to VNEG. Permanent device damage may occur if the maximum ratings
are exceeded. Functional operation should be restricted to those conditions specified in the operational sections of this
data sheet. Exposure to absolute maximum rating conditions for extended periods may adversely affect device
reliability.
2. VPOS is equal to VPOSF and VPOSS tied together for test condition purposes.
3. For more information regarding system-level ESD tolerance, refer to “AN315: Robust Electrical Surge Immunity for PoE
PDs through Integrated Protection”.
Table 3. Recommended Operating Conditions
Description
Symbol
Min
Typ
Max Units
|CT1 – CT2| or |SP1 – SP2|
VPORT
2.8
—
57
V
Ambient Operating Temperature
TA –40 25 85 °C
Note: Unless otherwise noted, all voltages referenced to VNEG. All minimum and maximum specifications are guaranteed
and apply across the recommended operating conditions. Typical values apply at nominal supply voltage and ambient
temperature unless otherwise noted.
Rev. 0.9
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
Si3400/Si3401
Table 9. Hotswap Interface Modes
Input Voltage (|CT1-
CT2| or |SP1-SP2|)
0 V to 2.7 V
2.7 V to 11 V
11 V to 14 V
14 V to 22 V
22 V to 42 V
42 V up to 57 V
57 V down to 36 V
Si3400 and Si3401
Mode
Inactive
Detection signature
Detection turns off and
internal bias starts
Classification signature
Transition region
Switcher operating mode
(hysteresis limit based on
rising input voltage)
Switcher operating mode
(hysteresis limit based on
falling input voltage)
3.2.1. Rectification Diode Bridges and
Surge Suppressor
The 802.3 specification defines the input voltage at the
RJ-45 connector of the PD with no reference to polarity.
In other words, the PD must be able to accept power of
either polarity at each of its inputs. This requirement
necessitates the use of two sets of diode bridges, one
for the CT1 and CT2 pins and one for the SP1 and SP2
pins to rectify the voltage. Furthermore, the standard
requires that a PD withstand a high-voltage transient
surge consisting of a 1000 V common-mode impulse
with 300 ns rise time and 50 µs half fall time. Typically,
the diode bridge and the surge suppressor have been
implemented externally, adding cost and complexity to
the PD system design.
The diode bridge* and the surge suppressor have been
integrated into the Si3400 and Si3401, thus reducing
system cost and design complexity.
*Note: Silicon Laboratories recommends that on-chip diode
bridges be bypassed when >10 W of output power is
required.
By integrating the diode bridges, the Si3400 and Si3401
gain access to the input side of the diode bridge.
Monitoring the voltage at the input of the diode bridges
instead of the voltage across the load capacitor
provides the earliest indication of a power loss. This true
early power loss indicator, PLOSS, provides a local
microcontroller time to save states and shut down
gracefully before the load capacitor discharges below
the minimum 802.3-specified operating voltage of 36 V.
Integration of the surge suppressor enables
optimization of the clamping voltage and guarantees
protection of all connected circuitry.
As an added benefit, the transient surge suppressor,
when tripped, actively disables the hotswap interface
and switching regulator, preventing downstream circuits
from encountering the high-energy transients.
3.2.2. Detection
In order to identify a device as a valid PD, a PSE will
apply a voltage in the range of 2.8 V to 10 V on the
cable and look for the 25.5 kΩ signature resistor. The
Si3400 and Si3401 will react to voltages in this range by
connecting an external 25.5 kΩ resistor between VPOS
and VNEG. This external resistor and internal low-
leakage control circuitry create the proper signature to
alert the PSE that a valid PD has been detected and is
ready to have power applied. The internal hotswap
switch is disabled during this time to prevent the
switching regulator and attached load circuitry from
generating errors in the detection signature.
Since the Si3400 and Si3401 integrate the diode
bridges, the IC can compensate for the voltage and
resistance effects of the diode bridges. The 802.3
specification requires that the PSE use a multi-point,
∆V/∆I measurement technique to remove the diode-
induced dc offset from the signature resistance
measurement. However, the specification does not
address the diode's nonlinear resistance and the error
induced in the signature resistor measurement. Since
the diode's resistance appears in series with the
signature resistor, the PD system must find some way of
compensating for this error. In systems where the diode
bridges are external, compensation is difficult and
suffers from errors. Since the diode bridges are
integrated in the Si3400 and Si3401, the IC can easily
compensate for this error by offsetting resistance across
all operating conditions and thus meeting the 802.3
requirements. An added benefit is that this function can
be tested during the IC’s automated testing step,
guaranteeing system compliance when used in the final
PD application. For more information about supporting
higher-power applications (above 12.95 W), see
“AN313: Using the Si3400 and Si3401 in High Power
Applications” and “AN314: Power Combining Circuit for
PoE for up to 18.5 W Output”.
3.2.3. Classification
Once the PSE has detected a valid PD, the PSE may
classify the PD for one of five power levels or classes. A
class is based on the expected power consumption of
the powered device. An external resistor sets the
nominal class current that can then be read by the PSE
to determine the proper power requirements of the PD.
When the PSE presents a fixed voltage between 15.5 V
and 20.5 V to the PD, the Si3400 and Si3401 assert the
class current from VPOS through the RCL resistor.
Rev. 0.9
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet SI3401.PDF ] | |
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