PDF SI4704-C40 Data sheet ( Hoja de datos )

Número de pieza	SI4704-C40
Descripción	(SI4704 / SI4705) BROADCAST FM RADIO RECEIVER
Fabricantes	Silicon Laboratories
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No Preview Available ! Si4704/05-C40 BROADCAST FM RADIO RECEIVER FOR CONSUMER ELECTRONICS Features  Worldwide FM band support  Programmable reference clock (64–108 MHz)  Volume control  Integrated antenna support  Adjustable soft mute control  EN55020 compliant  RDS/RBDS processor (Si4705)  Excellent real-world performance  Optional digital audio out (Si4705)  Freq synthesizer with integrated VCO  2-wire and 3-wire control interface  Advanced FM seek tuning  Integrated LDO regulator  Automatic frequency control (AFC)  Signal quality measurements  Automatic gain control (AGC)  2.7 to 5.5 V supply voltage  Digital FM stereo decoder  3x3 mm 20-pin QFN package  Minimal BOM  RoHS compliant  Programmable de-emphasis Applications  Table and portable radios  Stereos  Mini/micro systems  CD/DVD players  Boom boxes  Modules  Clock radios  Mini HiFi  Entertainment systems Description The Si4704/05 integrates all functions required for an advanced broadcast FM radio receiver, from antenna input to stereo audio output. Functional Block Diagram Ordering Information: See page 28. Pin Assignments Si4704/05-GM (Top View) NC 1 20 19 18 17 16 FMI 2 15 DOUT RFGND 3 LPI 4 GND PAD 14 LOUT 13 ROUT RST 5 12 GND 6 7 8 9 10 11 VDD FM Antenna FMI RFGND LPI 32.768 kHz RCLK 2.7–5.5 V VDD LNA AGC AFC REG 0/90 XTAL OSC Si4704/05 ADC DAC PGA DSP ADC DAC LOUT ROUT RSSI RDS (Si4705) CONTROL INTERFACE GPO DCLK DOUT DFS This product, its features, and/or its architecture is covered by one or more of the following patents, as well as other patents, pending and issued, both foreign and domestic: 7,127,217; 7,272,373; 7,272,375; 7,321,324; 7,355,476; 7,426,376; 7,471,940; 7,339,503; 7,339,504. Rev. 1.0 12/09 Copyright © 2009 by Silicon Laboratories Si4704/05-C40 Free Datasheet http://www.datasheet4u.com/ 1 page Si4704/05-C40 Table 3. DC Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max FM Receiver to Line Output Supply Current1 Supply Current2 RDS Supply Current1 IFM IFM Low SNR level IFM Supplies and Interface — 19.2 22 — 19.9 23 — 19.2 23 Interface Supply Current IIO — 320 600 VDD Powerdown Current IDDPD — 10 20 VIO Powerdown Current High Level Input Voltage3 Low Level Input Voltage3 High Level Input Current3 Low Level Input Current3 High Level Output Voltage4 Low Level Output Voltage4 IIOPD SCLK, RCLK inactive — 1 10 VIH 0.7 x VIO — VIO + 0.3 VIL –0.3 — 0.3 x VIO IIH VIN = VIO = 3.6 V –10 — 10 IIL VIN = 0 V, –10 — 10 VIO = 3.6 V VOH IOUT = 500 µA 0.8 x VIO — — VOL IOUT = –500 µA — — 0.2 x VIO Notes: 1. Guaranteed by characterization. 2. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions. 3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3. 4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3. Unit mA mA mA µA µA µA V V µA µA V V Rev. 1.0 5 Free Datasheet http://www.datasheet4u.com/ 5 Page Si4704/05-C40 Table 8. Digital Audio Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition DCLK Cycle Time DCLK Pulse Width High DCLK Pulse Width Low DFS Set-up Time to DCLK Rising Edge DFS Hold Time from DCLK Rising Edge DOUT Propagation Delay from DCLK Falling Edge tDCT tDCH tDCL tSU:DFS tHD:DFS tPD:DOUT Min 26 10 10 5 5 0 Typ Max Unit — 1000 ns — — ns — — ns — — ns — — ns — 12 ns DCLK DFS DOUT tDCH tDCL tDCT tHD:DFS tSU:DFS tPD:OUT Figure 8. Digital Audio Interface Timing Parameters, I2S Mode Rev. 1.0 11 Free Datasheet http:/ 11 Page

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