|
|
PDF AN1229 Data sheet ( Hoja de datos )
| Número de pieza | AN1229 | |
| Descripción | Class B Safety Software Library | |
| Fabricantes | Microchip | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AN1229 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
AN1229
Class B Safety Software Library for
PIC® MCUs and dsPIC® DSCs
Authors: Veena Kudva & Adrian Aur
Microchip Technology Inc.
INTRODUCTION
This application note describes the Class B Safety
Software Library routines that detect the occurrence of
Faults in a single channel CPU. These routines have
been developed in accordance with the IEC 60730
standard to support the Class B certification process.
These routines can be directly integrated with the end
user’s application to test and verify the critical
functionalities of a controller without affecting the end
user’s application.
This application note also describes the Application
Programming Interface (API) functions that are
available in the Class B Safety Software Library.
The Class B safety software routines can be called
periodically at start-up or run time to test the following
components:
• CPU Registers
• CPU Program Counter
• Invariable Memory
• Variable Memory
• Clock
• Interrupt Handling and Execution
This application note also outlines various techniques,
which are not part of the Class B Safety Software
Library, to test components such as external communi-
cation, timing, I/O periphery, analog I/O and analog
multiplexer.
Note:
The term ‘IEC 60730 standard’ used in
this document refers to the “IEC 60730-1
ed.3.2” Copyright © 2007 IEC, Geneva,
Switzerland. www.iec.ch.
OVERVIEW OF THE IEC 60730
STANDARD
Note:
“The author thanks the International Elec-
trotechnical Commission (IEC) for permis-
sion to reproduce information from its
International Standard IEC 60730-1ed.3.2
(2007). All such extracts are copyright of
IEC, Geneva, Switzerland. All rights
reserved. Further information on the IEC is
available from www.iec.ch. IEC has no
responsibility for the placement and con-
text in which the extracts and contents are
reproduced by the author, nor is IEC in any
way responsible for the other content or
accuracy therein.”
The IEC 60730 standard defines the test and diagnostic
methods that ensure the safe operation of the controlled
equipment used in household appliances. Annex H of
the IEC 60730 standard classifies the software into the
following categories (see Appendix B: “IEC 60730-1
Table H.11.12.7”):
• Class A
• Class B
• Class C
The Class B Safety Software Library implements the
important test and diagnostic methods that fall into the
Class B category. These methods use various
measures to detect and respond to the software-
related Faults and errors.
According to the IEC 60730 standard, the controls with
functions that fall into the Class B category should have
one of the following structures:
• Single Channel with Functional Test
In this structure, the Functional test is executed
prior to the application firmware execution.
• Single Channel with Periodic Self-Test
In this structure, the Periodic tests are embedded
within the firmware, and the self-test occurs
periodically while the firmware is in Execution
mode.
• Dual Channel without Comparison
In this structure, two independent methods execute
the specified operations.
2008-2012 Microchip Technology Inc.
DS01229C-page 1
Free Datasheet http://www.datasheet4u.com/
1 page  
Variable Memory Test
The Variable Memory test implements the Periodic
Static Memory test H.2.19.6 defined by the IEC 60730
standard. It detects single bit Faults in variable memory.
The variable memory contains data, which is intended to
vary during program execution. The RAM Memory test is
used to determine if any bit of the RAM memory is stuck
at ‘1’ or ‘0’. The March Memory test and Checkerboard
test are some of the widely used static memory
algorithms for checking the DC Faults.
The following tests can be implemented using the
Class B Safety Software Library:
• March Test
- March C Test
- March C Minus Test
- March B Test
MARCH TEST
A March test performs a finite set of operations on
every memory cell in a memory array. Each operation
performs the following tasks:
1. Writes ‘0’ to a memory cell (w0).
2. Writes ‘1’ to a memory cell (w1).
3. Reads the expected value ‘0’ from a memory
cell (r0).
4. Reads the expected value ‘1’ from a memory
cell (r1).
AN1229
March Test Notations
Figure 2 illustrates the notations that are used in the
March test.
FIGURE 2:
MARCH TEST NOTATIONS
: Arranges the address sequence in ascending
order.
: Arranges the address sequence in descending
order.
: Arranges the address sequence in either
ascending or descending order.
r 0 : Indicates a read operation (reads ‘0’ from a
memory cell).
r 1 : Indicates a read operation (reads ‘1’ from a
memory cell).
w 0 : Indicates a write operation (writes ‘0’ to a
memory cell).
w 1 : Indicates a write operation (writes ‘1’ to a
memory cell).
Note:
The March memory functions do not test
the Stack area of the RAM. The following
special functions are provided for the Stack
area test:
SSL_8bitsFamily_RAM_STACKtest_MarchC (PIC18)
SSL_16bitsFamily_RAM_STACKtest_MarchC
SSL_32bitsFamily_RAM_STACKtest_MarchC
2008-2012 Microchip Technology Inc.
DS01229C-page 5
Free Datasheet http://www.datasheet4u.com/
5 Page 
CLOCK TEST USING THE LINE FREQUENCY
(50 Hz, 60 Hz)
The Clock Test function is used to verify the proper
operation of the CPU clock. The 50 Hz/60 Hz line
frequency is used as an independent clock source or a
reference clock source. The input capture module is
used for the period measurement. The 50 Hz/60 Hz line
frequency is fed to the Input Capture pin (IC1) of the
respective device.
This test performs the following major tasks:
1. The IC1CON register is configured as follows:
a) Hardware Timer2 is selected as the IC1
time base (Timer1 for PIC18).
b) The capture operation is programmed to
occur on every rising edge of the line
frequency.
c) A capture done event (interrupt) is pro-
grammed to occur on every second capture
event
FIGURE 6:
TIMER VALUE CAPTURE
TMR2 or
TMR3
V1
V2
AN1229
2. The Timer2 prescaler is configured so that the
timer count does not time-out within 20 ms/
16.66 ms (Timer1 for PIC18).
3. The capture is performed on every rising edge of
line frequency. For period measurement, the
capture done event (interrupt) is generated after
taking two time-stamps (see Figure 6).
4. The difference between the two time-stamps
(V1 and V2) provides the timer period value.
The number of CPU cycles in 20 ms/16.66 ms of
the line frequency is computed as follows:
Number of Clock Cycles = ((V1 – V2) * Timer2
Prescaler)
API FUNCTIONS
The following API functions implement the Clock test:
• API Functions for 8-bit PIC MCUs (PIC18)
• SSL_16bitsFamily_CLOCKtest_LineFreq
• SSL_32bitsFamily_CLOCKtest_LineFreq
V3
V4
ICx
Capture
Event
Capture
Interrupt
(ICI<1:0> = 01)
Capture FIFO
V1
xxxx
xxxx
xxxx
1st Capture
Read Captured
Value in ISR
V1
V2
xxxx
xxxx
2nd Capture
V3
V2
xxxx
xxxx
3rd Capture
Note: In this illustration, the timer ramp is not to scale.
Read Captured
Value in ISR
V3
V4
xxxx
xxxx
4th Capture
2008-2012 Microchip Technology Inc.
DS01229C-page 11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AN1229.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AN1229 | Class B Safety Software Library | Microchip |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |