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AR9331 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AR9331
기능 Highly-Integrated and Cost Effective IEEE 802.11n 1x1 2.4 GHz SoC
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AR9331 데이터시트, 핀배열, 회로
Data Sheet
PRELIMINARY
December 2010
AR9331 Highly-Integrated and Cost Effective IEEE 802.11n
1x1 2.4 GHz SoC for AP and Router Platforms
General Description
The Atheros AR9331 is a highly integrated and
cost effective IEEE 802.11n 1x1 2.4 GHz System-
on-a-Chip (SoC) for wireless local area network
(WLAN) AP and router platforms.
In a single chip, the AR9331 includes a MIPS 24K
processor, five-port IEEE 802.3 Fast Ethernet
Switch with MAC/PHY, one USB 2.0 MAC/PHY,
and external memory interface for serial Flash,
SDRAM, DDR1 or DDR2, I2S/SPDIF-Out audio
interface, SLIC VOIP/PCM interface, UART, and
GPIOs that can be used for LED controls or other
general purpose interface configurations.
The AR9331 integrates two Gbit MACs plus a
five-port Fast Ethernet switch with a four-traffic
class Quality of Service (QoS) engine.
The AR9331 integrates an 802.11n 1x1 MAC/BB/
radio with internal PA and LNA. It supports
802.11n operations up to 72 Mbps for 20 MHz
and 150 Mbps for 40 MHz channel respectively,
and IEEE 802.11b/g data rates. Additional
features include on-chip one-time programmable
(OTP) memory.
System Block Diagram
Features
Complete IEEE 802.11n 1x1 AP or router in a
single chip
MIPS 24K processor operating at up to
400 MHz
External 16-bit DDR1, DDR2, or SDRAM
memory interface
SPI NOR Flash memory support
No external EEPROM needed
4 LAN ports and 1 WAN port IEEE 802.3 Fast
Ethernet switch with auto-crossover, auto
polarity, and auto-negotiation in PHYs
Four classes of QoS per port
Fully integrated RF front-end including PA
and LNA
Optional external LNA/PA
Switched antenna diversity
High-speed UART for console support
I2S/SPDIF-out audio interface
SLIC for VOIP/PCM
USB 2.0 host/device mode support
GPIO/LED support
JTAG-based processor debugging supported
25 MHz or 40 MHz reference clock input
Advanced power management with dynamic
clock switching for ultra-low power modes
148-pin, 12 mm x 12 mm dual-row LPCC
package
2.4 GHz
RF
Front
End
802.11n
1x1 WLAN
MAC/BB/
Radio
Internal
SRAM
I-Cache
D-Cache
AR9331
SDRAM/
DDR1/DDR2
Controller and
NOR Flash
Memory
Interface
MIPS 24K
Processor
5x Fast Ethernet
LAN/WAN Ports
UART
USB MAC/PHY
External Interface
I2S/SPDIF
SLIC
Serial Flash and SDRAM/DDR Interface
5x Fast Ethernet Ports
UART Interface
USB 2.0 Interface
GPIOs/LEDs
Audio Interface
VOIP/PCM
25 or 40 MHz Crystal
© 2010 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, No New Wires®,
Orion® , PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®, U-
Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™,
Ethos™, Install N Go™, IQUE™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The
Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
1
Free Datasheet http://www.datasheet4u.com/




AR9331 pdf, 반도체, 판매, 대치품
PRELIMINARY
(AHB_MASTER_TIMEOUT_CUR
NT) ................................................ 59
6.1.20 Timeout Slave Address
(AHB_MASTER_TIMEOUT_SLV_
ADDR) .......................................... 59
6.2 UART Registers ...................................... 60
6.2.1 UART Transmit and Rx FIFO
Interface (UART_DATA) ........... 60
6.2.2 UART Configuration and Status
(UART_CS) .................................. 61
6.2.3 UART Clock (UART_CLOCK) . 62
6.2.4 UART Interrupt/Control Status
(UART_INT) ................................ 62
6.2.5 UART Interrupt Enable
(UART_INT_EN) ........................ 63
6.3 USB Registers .......................................... 64
6.3.1 USB Power Control and Status
(USBPWRCTL) ............................ 64
6.3.2 USB Configuration
(USB_CONFIG) ........................... 64
6.4 GPIO Registers ....................................... 65
6.4.1 General Purpose I/O Output
Enable (GPIO_OE) ...................... 65
6.4.2 General Purpose I/O Input Value
(GPIO_IN) .................................... 65
6.4.3 General Purpose I/O Output Value
(GPIO_OUT) ................................ 65
6.4.4 General Purpose I/O Per Bit Set
(GPIO_SET) ................................. 66
6.4.5 General Purpose I/O Per Bit Clear
(GPIO_CLEAR) ........................... 66
6.4.6 General Purpose I/O Interrupt
Enable (GPIO_INT) .................... 66
6.4.7 General Purpose I/O Interrupt
Type (GPIO_INT_TYPE) ........... 66
6.4.8 General Purpose I/O Interrupt
Polarity (GPIO_INT_POLARITY)
66
6.4.9 General Purpose I/O Interrupt
Pending (GPIO_INT_PENDING) .
67
6.4.10 General Purpose I/O Interrupt
Mask (GPIO_INT_MASK) ......... 67
6.4.11 General Purpose I/O Function
(GPIO_FUNCTION_1) ............... 67
6.4.12 General Purpose I/O Input Value
(GPIO_IN_ETH_SWITCH_LED) 68
6.4.13 Extended GPIO Function Control
(GPIO_FUNCTION_2) .............. 69
6.5 PLL Control Registers ........................... 70
6.5.1 CPU Phase Lock Loop
Configuration
(CPU_PLL_CONFIG) ................. 70
6.5.2 CPU Phase Lock Loop
Configuration Register 2
(CPU_PLL_CONFIG2) ............... 70
6.5.3 CPU Clock Control Register
(CLOCK_CONTROL) ................ 71
6.5.4 CPU PLL Dither FRAC Register
(PLL_DITHER_FRAC) ............... 71
6.5.5 CPU PLL Dither Register
(PLL_DITHER) ............................ 72
6.5.6 Ethernet Switch Clock Control
Register (ETHSW_CLOCK
CONTROL) .................................. 72
6.5.7 Ethernet XMII Control Register
(ETH_XMII_CONTROL) ........... 73
6.5.8 Suspend Register (SUSPEND) .. 73
6.5.9 WLAN Clock Control Register
(WLAN_CLOCK_CONTROL) . 74
6.6 Reset Control Registers ......................... 75
6.6.1 General Purpose Timers
(RST_GENERAL_TIMER) ......... 75
6.6.2 General Purpose Timers Reload
(RST_GENERAL_TIMER_RELOA
D) .................................................. 75
6.6.3 Watchdog Timer Control Register
(RST_WATCHDOG_TIMER_CON
TROL) ........................................... 76
6.6.4 Watchdog Timer Register
(RST_WATCHDOG_TIMER) ... 76
6.6.5 Miscellaneous Interrupt Status
(RST_MISC_INTERRUPT_STATUS
) ...................................................... 77
6.6.6 Miscellaneous Interrupt Mask
(RST_MISC_INTERRUPT_MASK)
78
6.6.7 Global Interrupt Status
(RST_GLOBAL_INTERRUPT_STA
TUS) .............................................. 79
6.6.8 Reset (RST_RESET) .................... 80
6.6.9 Chip Revision ID
(RST_REVISION_ID) ................. 80
6.6.10 Bootstrap Status (BOOT_STRAP)
81
2 • AR9331 802.11n 1x1 2.4 GHz SoC for AP and Router Platforms
2 December 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Free Datasheet http://www.datasheet4u.com/

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AR9331 전자부품, 판매, 대치품
PRELIMINARY
(ISR_S5_S) .................................. 122
6.13 QCU Registers ..................................... 125
6.13.1 Tx Queue Descriptor (Q_TXDP) ...
125
6.13.2
QCU_STATUS_RING_START_AD
DRESS Lower 32 bits of Address
(Q_STATUS_RING_START) ... 126
6.13.3
QCU_STATUS_RING_END_ADD
R Lower 32 Bits of Address
(Q_STATUS_RING_END) ....... 126
6.13.4 QCU_STATUS_RING_CURRENT
Address
(Q_STATUS_RING_CURRENT) ..
126
6.13.5 Tx Queue Enable (Q_TXE) ...... 126
6.13.6 Tx Queue Disable (Q_TXD) .... 127
6.13.7 CBR Configuration (Q_CBRCFG)
127
6.13.8 ReadyTime Configuration
(Q_RDYTIMECFG) ................... 127
6.13.9 OneShotArm Set Control
(Q_ONESHOTARM_SC) ......... 128
6.13.10 OneShotArm Clear Control
(Q_ONESHOTARM_CC) ........ 128
6.13.11 Misc. QCU Settings (Q_MISC) 129
6.13.12 Misc. QCU Status (Q_STS) ..... 131
6.13.13 ReadyTimeShutdown Status
(Q_RDYTIMESHDN) ............... 131
6.13.14 Descriptor CRC Check
(MAC_QCU_DESC_CRC_CHK) ..
131
6.14 DCU Registers ..................................... 132
6.14.1 QCU Mask (D_QCUMASK) .... 132
6.14.2 DCU-Specific IFS Settings
(D_LCL_IFS) .............................. 133
6.14.3 Retry Limits (D_RETRY_LIMIT) ..
133
6.14.4 ChannelTime Settings
(D_CHNTIME) .......................... 134
6.14.5 Misc. DCU-Specific Settings
(D_MISC) ................................... 134
6.14.6 DCU-Global IFS Settings: SIFS
Duration (D_GBL_IFS_SIFS) ... 135
6.14.7 DCU-Global IFS Settings: Slot
Duration (D_GBL_IFS_SLOT) 135
6.14.8 DCU-Global IFS Settings: EIFS
Duration (D_GBL_IFS_EIFS) .. 135
6.14.9 DCU-Global IFS Settings: Misc.
Parameters (D_GBL_IFS_MISC) ..
136
6.14.10 DCU Tx Pause Control/Status
(D_TXPSE) ................................. 136
6.14.11 DCU Transmission Slot Mask
(D_TXSLOTMASK) .................. 137
6.15 Host Interface Registers ..................... 138
6.15.1 Reset the Host Interface
(HOST_INTF_RESET_CONTROL)
139
6.15.2 Host Timeout
(HOST_INTF_TIMEOUT) ....... 139
6.15.3 EEPROM Control
(HOST_INTF_EEPROM_CTRL) ..
139
6.15.4 MAC Silicon Revision ID
(HOST_INTF_SREV) ................ 139
6.15.5 Synchronous Interrupt Cause
(HOST_INTF_INTR_SYNC_CAUS
E) ................................................. 141
6.15.6 Synchronous Interrupt Enable
(HOST_INTF_INTR_SYNC_ENAB
LE) ............................................... 141
6.15.7 Asynchronous Interrupt Mask
(HOST_INTF_INTR_ASYNC_MAS
K) ................................................. 142
6.15.8 Synchronous Interrupt Mask
(HOST_INTF_INTR_SYNC_MASK
) ................................................... 142
6.15.9 Asynchronous Interrupt Cause
(HOST_INTF_INTR_ASYNC_CAU
SE) ............................................... 142
6.15.10 Asynchronous Interrupt Enable
(HOST_INTF_INTR_ASYNC_ENA
BLE) ............................................ 142
6.15.11 GPIO Output
(HOST_INTF_GPIO_OUT) ..... 143
6.15.12 GPIO Input
(HOST_INTF_GPIO_IN) ......... 143
6.15.13 Host GPIO Output Enable Bits
(HOST_INTF_GPIO_OE) ........ 144
6.15.14 Host GPIO Interrupt Polarity
(HOST_INTF_GPIO_INTR_POLAR
) ................................................... 144
6.15.15 GPIO Input Enable and Value
(HOST_INTF_GPIO_INPUT_VAL
UE) .............................................. 145
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9331 802.11n 1x1 2.4 GHz SoC for AP and Router Platforms • 5
December 2010 5
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AR9331

Highly-Integrated and Cost Effective IEEE 802.11n 1x1 2.4 GHz SoC

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