|
|
PDF XC17V00 Data sheet ( Hoja de datos )
| Número de pieza | XC17V00 | |
| Descripción | Configuration PROM | |
| Fabricantes | Xilinx | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de XC17V00 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
|
No Preview Available !
0
R XC17V00 Series Configuration
PROM
DS073 (v1.5) October 9, 2001
08
Features
• One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA devices
• Simple interface to the FPGA
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
• Low-power CMOS Floating Gate process
• 3.3V supply voltage
Advance Product Specification
• Available in compact plastic packages: VQ44, PC44,
PC20, VO8, and SO20
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages.
• Dual configuration modes for the XC17V16 and
XC17V08 devices
- Serial slow/fast configuration (up to 33 Mb/s)
- Parallel (up to 264 Mb/s at 33 MHz)
• Guaranteed 20 year life data retention
Description
Xilinx introduces the high-density XC17V00 family of config-
uration PROMs which provide an easy-to-use, cost-effec-
tive method for storing large Xilinx FPGA configuration
bitstreams. Initial devices in the 3.3V family are available in
16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. See Figure 1
and Figure 2 for simplified block diagrams of the XC17V00
family.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
When the FPGA is in SelectMAP mode, an external oscilla-
tor will generate the configuration clock that drives the
PROM and the FPGA. After the rising CCLK edge, data are
available on the PROMs DATA (D0-D7) pins. The data will
be clocked into the FPGA on the following rising edge of the
CCLK. A free-running oscillator may be used to drive CCLK.
See Figure 3.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to most commercial PROM programmers.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS073 (v1.5) October 9, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
1
Free Datasheet http://www.datasheet4u.com/
1 page  
R
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the three FPGA mode pins. In Master Serial
mode, the FPGA automatically loads the configuration pro-
gram from an external memory. The Xilinx PROMs have
been designed for compatibility with the Master Serial
mode.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA
mode-select pins are Low (M0=0, M1=0, M2=0). Data is
read from the PROM sequentially on a single data line. Syn-
chronization is provided by the rising edge of the temporary
signal CCLK, which is generated during configuration.
Master Serial Mode provides a simple configuration inter-
face. Only a serial data line, two control lines, and a clock
line are required to configure an FPGA. Data from the
PROM is read sequentially, accessed via the internal
XC17V00 Series Configuration PROM
address and bit counters which are incremented on every
valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the
FPGA is used only for configuration, it must still be held at a
defined level during normal operation. The Xilinx FPGA
families take care of this automatically with an on-chip
default pull-up/down resistor or keeper circuit.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded PROMs provide additional memory. After the last bit
from the first PROM is read, the next clock signal to the
PROM asserts its CEO output Low and disables its DATA
line. The second PROM recognizes the Low level on its CE
input and enables its DATA output. See Figure 3.
After configuration is complete, the address counters of all
cascaded PROMs are reset if the FPGA PROGRAM pin
goes Low, assuming the PROM reset polarity option has
been inverted.
DS073 (v1.5) October 9, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
R XC17V00 Series Configuration PROM
AC Characteristics Over Operating Condition When Cascading
OE/RESET
CE
CLK
DATA
CEO
TCDF
Last Bit
TOCK
TOCE
TOOE
Symbol
Description
Min Max
Units
TCDF
TOCK
TOCE
TOOE
CLK to data float delay(2,3)
CLK to CEO delay(3)
CE to CEO delay(3)
RESET/OE to CEO delay(3)
- 50
- 30
- 35
- 30
ns
ns
ns
ns
Notes:
1. AC test load = 50 pF
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady
state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
First Bit
DS026_07_020300
DS073 (v1.5) October 9, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet XC17V00.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| XC17V00 | Configuration PROM | Xilinx |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |