CAV24C04 Datasheet PDF - ON Semiconductor
| Part Number | CAV24C04 | |
| Description | (CAV24C02 - CAV24C16) I2C CMOS Serial EEPROM | |
| Manufacturers | ON Semiconductor | |
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CAV24C02, CAV24C04,
CAV24C08, CAV24C16
2-Kb, 4-Kb, 8-Kb and 16-Kb
I2C CMOS Serial EEPROM
Description
The CAV24C02/04/08/16 are 2−Kb, 4−Kb, 8−Kb and 16−Kb
respectively CMOS Serial EEPROM devices organized internally as
16/32/64 and 128 pages respectively of 16 bytes each. All devices
support both the Standard (100 kHz) as well as Fast (400 kHz) I2C
protocol.
Data is written by providing a starting address, then loading 1 to 16
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address up to eight
CAV24C02, four CAV24C04, two CAV24C08 and one CAV24C16
device on the same bus.
Features
• Automotive Temperature Grade 1 (−40°C to +125°C)
• Supports Standard and Fast I2C Protocol
• 2.5 V to 5.5 V Supply Voltage Range
• 16−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
• CAV Prefix for Automotive and Other Applications Requiring Site
and Change Control
• Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
• Low power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
VCC
SCL
A2, A1, A0
WP
CAV24Cxx
SDA
VSS
Figure 1. Functional Symbol
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
www.onsemi.com
TSSOP−8
Y SUFFIX
CASE 948AL
SOIC−8
W SUFFIX
CASE 751BD
WLCSP−4***
C4A SUFFIX
CASE 567DC
WLCSP−5***
C5A SUFFIX
CASE 567DD
PIN CONFIGURATIONS
SOIC (W), TSSOP (Y)
CAV24C__
16 / 08 / 04 / 02
NC / NC / NC / A0
NC / NC / A1 / A1
NC / A2 / A2 / A2
VSS
18
27
36
45
(Top View)
Pin 1 1
2 Pin 1 1 2
VCC
WP
SCL
SDA
3
A VCC
VSS
B SCL SDA
VCC
VSS
SDA
A
B
WP SCL C
WLCSP−4***
WLCSP−5***
(Top Views)
PIN FUNCTION
Pin Name
A0, A1, A2
Function
Device Address Input
SDA
Serial Data Input/Output
SCL Serial Clock Input
WP Write Protect Input
VCC Power Supply
VSS Ground
NC No Connect
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 4
1
Publication Order Number:
CAV24C02/D
|
| |
 
CAV24C02, CAV24C04, CAV24C08, CAV24C16
Power−On Reset (POR)
Each CAV24Cxx* incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
A CAV24Cxx device will power up into Standby mode
after VCC exceeds the POR trigger level and will power
down into Reset mode when VCC drops below the POR
trigger level. This bi−directional POR feature protects the
device against ‘brown−out’ failure following a temporary
loss of power.
*For common features, the CAV24C02/04/08/16 will be
referred to as CAV24Cxx.
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2: The Address inputs set the device address
when cascading multiple devices. When not driven, these
pins are pulled LOW internally.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
Functional Description
The CAV24Cxx supports the Inter−Integrated Circuit
(I2C) Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAV24Cxx acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver.
I2C Bus Protocol
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pull−up
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see AC Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is high. An SDA transition while SCL is
high will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake−up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. For normal Read/Write operations, the
first 4 bits of the Slave address are fixed at 1010 (Ah). The
next 3 bits are used as programmable address bits when
cascading multiple devices and/or as internal address bits.
The last bit of the slave address, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed. The 3
address space extension bits are assigned as illustrated in
Figure 3. A2, A1 and A0 must match the state of the external
address pins, and a10, a9 and a8 are internal address bits.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge the address byte and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9th clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.
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