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CAV24C08 데이터시트 PDF




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부품번호 CAV24C08 기능
기능 (CAV24C02 - CAV24C16) I2C CMOS Serial EEPROM
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CAV24C08 데이터시트, 핀배열, 회로
CAV24C02, CAV24C04,
CAV24C08, CAV24C16
2-Kb, 4-Kb, 8-Kb and 16-Kb
I2C CMOS Serial EEPROM
Description
The CAV24C02/04/08/16 are 2−Kb, 4−Kb, 8−Kb and 16−Kb
respectively CMOS Serial EEPROM devices organized internally as
16/32/64 and 128 pages respectively of 16 bytes each. All devices
support both the Standard (100 kHz) as well as Fast (400 kHz) I2C
protocol.
Data is written by providing a starting address, then loading 1 to 16
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address up to eight
CAV24C02, four CAV24C04, two CAV24C08 and one CAV24C16
device on the same bus.
Features
Automotive Temperature Grade 1 (−40°C to +125°C)
Supports Standard and Fast I2C Protocol
2.5 V to 5.5 V Supply Voltage Range
16−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
CAV Prefix for Automotive and Other Applications Requiring Site
and Change Control
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
VCC
SCL
A2, A1, A0
WP
CAV24Cxx
SDA
VSS
Figure 1. Functional Symbol
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
www.onsemi.com
TSSOP−8
Y SUFFIX
CASE 948AL
SOIC−8
W SUFFIX
CASE 751BD
WLCSP−4***
C4A SUFFIX
CASE 567DC
WLCSP−5***
C5A SUFFIX
CASE 567DD
PIN CONFIGURATIONS
SOIC (W), TSSOP (Y)
CAV24C__
16 / 08 / 04 / 02
NC / NC / NC / A0
NC / NC / A1 / A1
NC / A2 / A2 / A2
VSS
18
27
36
45
(Top View)
Pin 1 1
2 Pin 1 1 2
VCC
WP
SCL
SDA
3
A VCC
VSS
B SCL SDA
VCC
VSS
SDA
A
B
WP SCL C
WLCSP−4***
WLCSP−5***
(Top Views)
PIN FUNCTION
Pin Name
A0, A1, A2
Function
Device Address Input
SDA
Serial Data Input/Output
SCL Serial Clock Input
WP Write Protect Input
VCC Power Supply
VSS Ground
NC No Connect
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 4
1
Publication Order Number:
CAV24C02/D




CAV24C08 pdf, 반도체, 판매, 대치품
CAV24C02, CAV24C04, CAV24C08, CAV24C16
Table 5. A.C. CHARACTERISTICS (Note 6) (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Standard
Fast
Symbol
Parameter
Min Max Min Max
FSCL
Clock Frequency
100 400
tHD:STA
START Condition Hold Time
4 0.6
tLOW
Low Period of SCL Clock
4.7 1.3
tHIGH
High Period of SCL Clock
4 0.6
tSU:STA
START Condition Setup Time
4.7 0.6
tHD:DAT
Data In Hold Time
00
tSU:DAT
Data In Setup Time
250 100
tR SDA and SCL Rise Time
1000
300
tF (Note 6)
SDA and SCL Fall Time
300 300
tSU:STO
STOP Condition Setup Time
4 0.6
tBUF Bus Free Time Between STOP and START
4.7 1.3
tAA SCL Low to Data Out Valid
3.5 0.9
tDH Data Out Hold Time
100 100
Ti (Note 6)
Noise Pulse Filtered at SCL and SDA Inputs
100 100
tSU:WP
WP Setup Time
00
tHD:WP
WP Hold Time
2.5 2.5
tWR Write Cycle Time
55
tPU (Notes 7, 8) Power−up to Ready Mode
6. Test conditions according to “AC Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
0.1
0.1
Table 6. A.C. TEST CONDITIONS
Input Drive Levels
Input Rise and Fall Time
0.2 x VCC to 0.8 x VCC
v 50 ns
Input Reference Levels
Output Reference Level
Output Test Load
0.3 x VCC, 0.7 x VCC
0.5 x VCC
Current Source IOL = 3 mA; CL = 100 pF
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms
ms
ms
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CAV24C08 전자부품, 판매, 대치품
CAV24C02, CAV24C04, CAV24C08, CAV24C16
WRITE OPERATIONS
Byte Write
In Byte Write mode, the Master sends the START
condition and the Slave address with the R/W bit set to zero
to the Slave. After the Slave generates an acknowledge, the
Master sends the byte address that is to be written into the
address pointer of the CAV24Cxx. After receiving another
acknowledge from the Slave, the Master transmits the data
byte to be written into the addressed memory location. The
CAV24Cxx device will acknowledge the data byte and the
Master generates the STOP condition, at which time the
device begins its internal Write cycle to nonvolatile memory
(Figure 6). While this internal cycle is in progress (tWR), the
SDA output will be tri−stated and the CAV24Cxx will not
respond to any request from the Master device (Figure 7).
Page Write
The CAV24Cxx writes up to 16 bytes of data in a single
write cycle, using the Page Write operation (Figure 8). The
Page Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating after
the data byte is transmitted, the Master is allowed to send up
to fifteen additional bytes. After each byte has been
transmitted the CAV24Cxx will respond with an
acknowledge and internally increments the four low order
address bits. The high order bits that define the page address
remain unchanged. If the Master transmits more than sixteen
bytes prior to sending the STOP condition, the address
counter ‘wraps around’ to the beginning of page and
previously transmitted data will be overwritten. Once all
sixteen bytes are received and the STOP condition has been
sent by the Master, the internal Write cycle begins. At this
point all received data is written to the CAV24Cxx in a single
write cycle.
Acknowledge Polling
The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAV24Cxx initiates the internal write cycle.
The ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAV24Cxx is still busy
with the write operation, NoACK will be returned. If the
CAV24Cxx has completed the internal write operation, an
ACK will be returned and the host can then proceed with the
next read or write operation.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAV24Cxx. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAV24Cxx will not acknowledge the data byte
and the Write request will be rejected.
Delivery State
The CAV24Cxx is shipped erased, i.e., all bytes are FFh.
BUS ACTIVITY:
MASTER
SLAVE
S
T
A SLAVE
R ADDRESS
T
S
ADDRESS
BYTE
a7 − a0
AA
CC
KK
Figure 6. Byte Write Sequence
DATA
BYTE
d7 − d0
S
T
O
P
P
A
C
K
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