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PDF ADV8003 Data sheet ( Hoja de datos )

Número de pieza ADV8003
Descripción Video Signal Processor
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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Data Sheet
NatureVue™ Video Signal Processor with
Bitmap OSD, Dual HDMI Tx, and Encoder
ADV8003
FEATURES
Video signal processor
Full 12-bit, 4:4:4 YUV internal processing
Motion adaptive de-interlacing with ultralow angle
interpolation
Multiple video processing paths
Upscaling to 4k × 2k (ADV8003KBCZ-8x models only)
Aspect ratio conversion/panorama scaling
Cadence detection for the recovery of original frames from
film-based content
Dual video scalers enable simultaneous output of multiple
different resolutions
Sharpness and detail enhancement
Noise reduction to reduce random, mosquito, and block
noise
Frame rate converter
Support for up to 3 simultaneous video streams, including
picture-in-picture (PiP) support
On-screen display (OSD)
Internally generated bitmap-based OSD allowing overlay
on one or more video outputs
Overlay on 3D video formats
Dedicated OSD scaler
Alpha blending of OSD data on video data
Disturbance free blending of OSD on either of 2 zones
Option of external OSD
Easy to use software tool for developing OSDs
HDMI transmitters
Dual HDMI transmitters enabling splitter capability
Content type bits
CEC 1.4 controller
Audio return channel (ARC) support
Support of standard S/PDIF for stereo LPCM compressed
audio up to 192 kHz
6-channel uncompressed LPCM I2S audio up to 192 kHz
6-channel direct stream digital (DSD) audio inputs
Noise shaped video (NSV) six-DAC video encoder
Six 12-bit NSV video DACs
Multiformat video output support
Composite (CVBS), S-Video (Y/C), and Component YPrPb
(SD, ED, and HD)
Rovi Rev. 7.1.L1 (SD) and Rev. 1.4 (ED) compliant
Simultaneous SD and ED/HD operation
Professional video mode
Capability to output up to 36-bit TTL data
APPLICATIONS
High-end A/V receivers
Upconverting DVD players/recorders
Blu-ray players/recorders
Set-top boxes
Video conferencing
Standalone video processors
HDMI splitters
TTL DATA
ADV8003
60-BIT
TTL PORT
24-BIT/
36-BIT/
48-BIT
VIDEO
INPUT
36-BIT
VIDEO
OUTPUT
SERIAL VIDEO
FOR EXAMPLE, ADV78500
OUTPUT
SERIAL
VIDEO
RECEIVER
FUNCTIONAL BLOCK DIAGRAM
DDR2 INTERFACE
AUDIO INPUT
LOW ANGLE
PROCESSING
CADENCE
DETECTION
MOTION
DETECTION
CUE
CORRECTION
DE-INTERLACER
DETAIL
ENHANCE
NOISE
REDUCTION
ENHANCE
VIDEO PROCESSING
OSD BUILD
AND SCALE
DUAL SCALER
AND
OSD BLEND
FRC
HDMI Tx1
HDMI Tx2
HD VIDEO
DACs
SD VIDEO
DACs
HDMI
HDMI
HD VIDEO
SD VIDEO
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.datasheet4u.com/

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ADV8003 pdf
Data Sheet
DETAILED FUNCTIONAL BLOCK DIAGRAM
DSD_CLK
AUD_IN[5:0]
SCLK
MCLK
DDR_VREF
DDR_CK
DDR_CK
DDR_CS
DDR_WE
DDR_RAS
DDR_CAS
DDR_A[12:0]
DDR_BA[2:0]
DDR_DM[3:0]
DDR_DQS[3:0]
DDR_DQS[3:0]
DDR_DQ[31:0]
Figure 3. ADV8003KBCZ-8
Rev. B | Page 5 of 64
ADV8003
COMPx
RSETx
VREF
ELPFx
SFL
ALSB
SCL
SDA
CS2
SCK2
MISO2
MOSI2
CS1
SCK1
MISO1
MOSI1
HEAC_1–
HEAC_1+
HEAC_2–
HEAC_2+
ARC1_OUT
ARC2_OUT
DVDD_IO
PVDD_DDR
DVDD_DDR
AVDDx
CVDD1
PVDDx
DVDD
PDN
RESET
Free Datasheet http://www.datasheet4u.com/

5 Page





ADV8003 arduino
Data Sheet
ADV8003
Parameter
VIDEO DATA AND CONTROL OUTPUTS3
OSD_CLK High Time
OSD_CLK Low Time
OSD_CLK Active Edge to Data and Control
Start of Data Invalid (Data Latched on Falling
Edge)
OSD_CLK Active Edge to Data and Control End
of Data Invalid (Data Latched on Falling Edge)
OSD_CLK Active Edge to Data and Control
Start of Data Invalid (Data Latched on Rising
Edge)
OSD_CLK Active Edge to Data and Control End
of Data Invalid (Data Latched on Rising Edge)
S/PDIF INPUT3
MCLK High Time
Symbol
t56
t57
t58
t59
t60
t61
Test Conditions/Comments
Min
0.40 ×
OSD_CLK
period
0.40 ×
OSD_CLK
period
0.45 × MCLK
periods
Typ
MCLK Low Time
0.45 × MCLK
periods
S/PDIF Data Setup Time
S/PDIF Data Hold Time
I2S PORT, SLAVE MODE3
SCLK High Time
t62
t63
t64
0.12
1.89
0.45 × SCLK
periods
SCLK Low Time
0.45 × SCLK
periods
I2S Data Setup Time
I2S Data Hold Time
DSD PORT3
DSD Clock High Time
t65
t66
t67
0.42
1.38
0.45 × DSD
CLK periods
DSD Clock Low Time
0.45 × SCLK
periods
DSD Data Setup Time
DSD Data Hold Time
t68
t69
0.48
1.79
1 It is possible to run I2C at faster speeds; however, it has been characterized to run only in fast mode.
2 All serial port measurements are for the default polarity and phase settings (clock low in idle state and negative edge used).
3 All measurements are guaranteed by design only.
Timing Diagrams
SDA
SCL
t3 t5 t3
t6 t1
t2 t7
Figure 4. I2C Timing
Rev. B | Page 11 of 64
t4
t8
Max Unit
0.60 ×
OSD_CLK
period
0.60 ×
OSD_CLK
period
0.07
%
duty
cycle
%
duty
cycle
ns
1.56 ns
0.41 ns
0.93 ns
0.55 ×
MCLK
periods
0.55 ×
MCLK
periods
%
duty
cycle
%
duty
cycle
ns
ns
0.55 ×
SCLK
periods
0.55 ×
SCLK
periods
%
duty
cycle
%
duty
cycle
ns
ns
0.55 ×
DSDCLK
periods
0.55 × SCLK
periods
%
duty
cycle
%
duty
cycle
ns
ns
Free Datasheet http://www.datasheet4u.com/

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