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AD9106 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9106은 전자 산업 및 응용 분야에서
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부품번호 AD9106 기능
기능 Digital-to-Analog Converter and Waveform Generator
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AD9106 데이터시트, 핀배열, 회로
Data Sheet
Quad, Low Power, 12-Bit, 180 MSPS, Digital-to-
Analog Converter and Waveform Generator
AD9106
FEATURES
Highly integrated quad DAC
On-chip 4096 × 12-bit pattern memory
On-chip DDS
Power dissipation at 3.3 V, 4 mA output
315 mW at 180 MSPS
Sleep mode: < 5 mW at 3.3 V
Supply voltage: 1.8 V to 3.3 V
SFDR to Nyquist
86 dBc at 1 MHz output
85 dBc at 10 MHz output
Phase noise at 1 kHz offset, 180 MSPS, 8 mA: −140 dBc/Hz
Differential current outputs: 8 mA maximum at 3.3 V
Small footprint 32-lead, 5 mm × 5 mm with 3.5 mm ×
3.6 mm exposed paddle LFCSP
Pb-free package
APPLICATIONS
Medical instrumentation
Ultrasound transducer excitation
Portable instrumentation
Signal generators, arbitrary waveform generators
GENERAL DESCRIPTION
The AD9106 TxDAC® and waveform generator is a high perform-
ance quad DAC integrating on-chip pattern memory for complex
waveform generation with a direct digital synthesizer (DDS). The
DDS is a 12-bit output, up to 180 MHz master clock sinewave
generator with a 24-bit tuning word allowing 10.8 Hz/LSB
frequency resolution. The DDS has a single frequency output
for all four DACs and independent programmable phase shift
outputs for each of the four DACs.
SRAM data can include directly generated stored waveforms,
amplitude modulation patterns applied to DDS outputs, or
DDS frequency tuning words.
An internal pattern control state machine allows the user to
program the pattern period for all four DACs as well as the start
delay within the pattern period for the signal output on each
DAC channel.
An SPI interface is used to configure the digital waveform
generator and load patterns into the SRAM.
There are gain adjustment factors and offset adjustments
applied to the digital signals on their way into the four DACs.
The AD9106 offers exceptional ac and dc performance and
supports DAC sampling rates up to 180 MSPS. The flexible
power supply operating range of 1.8 V to 3.3 V and low power
dissipation of the AD9106 make it well suited for portable and low
power applications.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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AD9106 pdf, 반도체, 판매, 대치품
AD9106
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS (3.3 V)
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V; internal CLDO, DLDO1, and DLDO2; IOUTFS = 4 mA, maximum sample rate,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY at 3.3 V
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
DAC OUTPUTS
Offset Error
Gain Error Internal Reference—No Automatic IOUTFS Calibration
Full-Scale Output Current1 at 3.3 V
Output Resistance
Output Compliance Voltage
Crosstalk, DAC to DAC (fOUT = 10 MHz)
Crosstalk, DAC to DAC (fOUT = 60 MHz)
DAC TEMPERATURE DRIFT
Gain with Internal Reference
Internal Reference Voltage
REFERENCE OUTPUT
Internal Reference Voltage with AVDD = 3.3 V
Output Resistance
REFERENCE INPUT
Voltage Compliance
Input Resistance External, Reference Mode
DAC MATCHING
Gain Matching—No Automatic IOUTFS Calibration
Min Typ
12
±0.4
±0.5
±.00025
−1.0
24
200
−0.5
96
82
±251
±119
0.8 1.0
10
0.1
1
±0.75
Max Unit
Bits
LSB
LSB
% of FSR
+1.0 % of FSR
8 mA
MΩ
+1.0 V
dBC
dBc
ppm/°C
ppm/°C
1.2 V
1.25 V
% of FSR
1 Based on use of 8 kΩ external xRSET resistors.
Rev. A | Page 4 of 48
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AD9106 전자부품, 판매, 대치품
Data Sheet
INPUT/OUTPUT SIGNAL SPECIFICATIONS
Table 5.
Parameter
CMOS INPUT LOGIC LEVEL (SCLK, CSE, SDIO, SDO/SDI2/DOUT, RESETE,
AA
AA
TRIGGERE)
AA
Input VIN Logic High
Input VIN Logic Low
CMOS OUTPUT LOGIC LEVEL (SDIO, SDO/SDI2/DOUT)
Output VOUT Logic High
Output VOUT Logic Low
DAC CLOCK INPUT (CLKP, CLKN)
Minimum Peak-to-Peak Differential Input Voltage, VCLKP/VCLKN
Maximum Voltage at VCLKP or VCLKN
Minimum Voltage at VCLKP or VCLKN
Common-Mode Voltage Generated on Chip
Test Conditions/ Comments
DVDD = 1.8 V
DVDD = 3.3 V
DVDD = 1.8 V
DVDD = 3.3 V
DVDD = 1.8 V
DVDD = 3.3 V
DVDD = 1.8 V
DVDD = 3.3 V
AD9106
Min Typ Max Unit
1.53
2.475
0.27
0.825
V
V
V
V
1.79 V
3.28 V
0.25 V
0.625 V
150
VDVDD
VDGND
0.9
mV
V
V
V
Rev. A | Page 7 of 48
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