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부품번호 | AD9129 기능 |
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기능 | (AD9119 / AD9129) RF Digital-to-Analog Converter | ||
제조업체 | Analog Devices | ||
로고 | |||
전체 68 페이지수
Data Sheet
FEATURES
DAC update rate: up to 5.6 GSPS
Direct RF synthesis at 2.8 GSPS data rate
DC to 1.4 GHz in baseband mode
DC to 1.0 GHz in 2× interpolation mode
1.4 GHz to 4.2 GHz in Mix-Mode
Bypassable 2× interpolation
Excellent dynamic performance
Supports DOCSIS 3.0 wideband ACLR/harmonic performance
8 QAM carriers: ACLR > 65 dBc
Industry-leading single/multicarrier IF or RF synthesis
4-carrier W-CDMA ACLR at 2457.6 MSPS
fOUT = 900 MHz, ACLR = 71 dBc (baseband mode)
fOUT = 2100 MHz, ACLR = 68 dBc (Mix-Mode)
fOUT = 2700 MHz, ACLR = 67 dBc (Mix-Mode)
Dual-port LVDS and DHSTL data interface
Up to 1.4 GSPS operation
Source synchronous DDR clocking with parity bit
Low power: 1.0 W at 2.8 GSPS (1.3 W at 5.6 GSPS)
APPLICATIONS
Broadband communications systems
CMTS/VOD
Wireless infrastructure: W-CDMA, LTE, point-to-point
Instrumentation, automatic test equipment (ATE)
Radars, jammers
GENERAL DESCRIPTION
The AD9119/AD9129 are high performance, 11-/14-bit RF digital-
to-analog converters (DACs) supporting data rates up to 2.8 GSPS.
The DAC core is based on a quad-switch architecture that enables
dual-edge clocking operation, effectively increasing the DAC
update rate to 5.6 GSPS when configured for Mix-Mode™ or 2×
interpolation. The high dynamic range and bandwidth enable
multicarrier generation up to 4.2 GHz.
In baseband mode, wide bandwidth capability combines with high
dynamic range to support from 1 to 158 contiguous carriers for
CATV infrastructure applications. A choice of two optional 2×
interpolation filters is available to simplify the postreconstruction
filter by effectively increasing the DAC update rate by a factor of 2.
In Mix-Mode operation, the AD9119/AD9129 can reconstruct
RF carriers in the second and third Nyquist zone while still
maintaining exceptional dynamic range up to 4.2 GHz. The
high performance NMOS DAC core features a quad-switch
architecture that enables industry-leading direct RF synthesis
performance with minimal loss in output power. The output
current can be programmed over a range of 9.5 mA to 34.4 mA.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
11-/14-Bit, 5.6 GSPS,
RF Digital-to-Analog Converter
AD9119/AD9129
FUNCTIONAL BLOCK DIAGRAM
RESET
IRQ
I250U VREF
SDIO
SDO
CS
SCLK
FRM_x
(FRAME/
PARITY)
P0_D[13:0]P,
P0_D[13:0]N
DCI_x
SPI
DLL
AD9129
1.2V
MIX-
NORMAL MODE
BASEBAND
MODE
Tx DAC
CORE
2×
IOUTP
IOUTN
P1_D[13:0]P,
P1_D[13:0]N
PLL
DCO_x
CLOCK
DISTRIBUTION
Figure 1.
DCR
DACCLK_x
The AD9119/AD9129 include several features that may further
simplify system integration. A dual-port, source synchronous
LVDS interface simplifies the data interface to a host FPGA/ASIC.
A differential frame/parity bit is also included to monitor the
integrity of the interface. On-chip delay locked loops (DLLs)
are used to optimize timing between different clock domains.
A serial peripheral interface (SPI) is used to configure the
AD9119/AD9129 and monitor the status of readback registers.
The AD9119/AD9129 is manufactured on a 0.18 µm CMOS
process and operates from +1.8 V and −1.5 V supplies. It is
supplied in a 160-ball chip scale package ball grid array.
PRODUCT HIGHLIGHTS
1. High dynamic range and signal reconstruction bandwidth
support RF signal synthesis of up to 4.2 GHz.
2. Dual-port interface with double data rate (DDR) LVDS
data receivers supports 2800 MSPS maximum conversion rate.
3. Manufactured on a CMOS process; a proprietary switching
technique enhances dynamic performance.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.datasheet4u.com/
AD9119/AD9129
Data Sheet
LVDS DIGITAL SPECIFICATIONS
VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C. LVDS drivers and receivers are compatible with the IEEE
Standard 1596.3-1996, unless otherwise noted.
Table 2.
Parameter
LVDS DATA INPUTS (P1_D[13:0]P, P1_D[13:0]N,
P0_D[13:0]P, P0_D[13:0]N)
Input Voltage Range
Input Differential Threshold
Input Differential Hysteresis
Receiver Differential Input Impedance
LVDS Input Rate
Input Capacitance
LVDS CLOCK INPUTS (DCI_P, DCI_N)
Input Voltage Range
Input Differential Threshold
Input Differential Hysteresis
Receiver Differential Input Impedance
Maximum Clock Rate
LVDS CLOCK OUTPUTS (DCO_P, DCO_N)
Output Voltage High
Output Voltage Low
Output Differential Voltage
Output Offset Voltage
Output Impedance, Single-Ended
RO Mismatch Between A and B
Change in |VOD| Between Setting 0 and Setting 1
Change in VOS Between Setting 0 and Setting 1
Output Current
Driver Shorted to Ground
Drivers Shorted Together
Power-Off Output Leakage
Maximum Clock Rate
Symbol
Test Conditions/Comments
Px_DxP = VIA, Px_DxN = VIB
VIA, VIB
VIDTH
VIDTHH − VIDTHL
RIN
Min
825
−100
80
1400
VIA, VIB
VIDTH
VIDTHH − VIDTHL
RIN
VOA, VOB
VOA, VOB
|VOA|, |VOB|
VOS
RO
∆RO
|∆VOD|
∆VOS
DCI_P = VIA, DCI_N = VIB
DCO_P = VOA, DCO_N = VOB,
100 Ω termination
Register 0x7C[7:6] = 01b (default)
825
−225
80
700
1025
200
1150
80
ISA, ISB
ISAB
|IXA|, |IXB|
700
Typ Max Unit
1575 mV
+100 mV
20 mV
120 Ω
MSPS
1.2 pF
1575 mV
+225 mV
20 mV
120 Ω
MHz
1375 mV
mV
225 250 mV
1250 mV
100 120 Ω
10 %
25 mV
25 mV
20 mA
4 mA
10 µA
MHz
HSTL DIGITAL SPECIFICATIONS
VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C. HSTL receiver levels are compatible with the EIA/JEDEC
JESD8-6 standard, unless otherwise noted.
Table 3.
Parameter
HSTL DATA INPUTS (P1_D[13:0]P, P1_D[13:0]N,
P0_D[13:0]P, P0_D[13:0]N)
Common-Mode Input Voltage Range
Differential Input Voltage
Receiver Differential Input Impedance
HSTL Input Rate
Input Capacitance
HSTL CLOCK INPUT (DCI_P, DCI_N)
Common-Mode Input Voltage Range
Differential Input Voltage
Receiver Differential Input Impedance
Maximum Clock Rate
Symbol
VIA, VIB
RIN
VIA, VIB
RIN
Test Comments/Conditions
Px_DxP = VIA, Px_DxN = VIB
Min
0.68
200
80
DCI_P = VIA, DCI_N = VIB
0.68
450
80
700
Typ Max Unit
0.9
1400
1.2
120
V
mV
Ω
MSPS
pF
0.9 mV
mV
120 Ω
MHz
Rev. 0 | Page 4 of 68
Free Datasheet http://www.datasheet4u.com/
4페이지 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
DCI, DCO to VSS
LVDS Data Inputs to VSS
IOUTP, IOUTN to VSSA
I250U, VREF to VSSA
IRQ, CS, SCLK, SDO, SDIO, RESET,
SYNC to VSS
Junction Temperature
Operating Temperature Range
Storage Temperature Range
Rating
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
VSSA − 0.3V to +2.5V
VSSA − 0.3 V to VDDA + 0.3 V
−0.3 V to VDD + 0.3 V
150°C
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AD9119/AD9129
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
Package Type
θJA
160-Ball CSP_BGA
31.2
θJC
7.0
Unit
°C/W1
1 With no airflow movement.
ESD CAUTION
Rev. 0 | Page 7 of 68
Free Datasheet http://www.datasheet4u.com/
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