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ADC081S051 데이터시트 PDF




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부품번호 ADC081S051 기능
기능 8-Bit A/D Converter
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ADC081S051 데이터시트, 핀배열, 회로
April 2005
ADC081S051
Single Channel, 500 kSPS, 8-Bit A/D Converter
General Description
The ADC081S051 is a low-power, single channel CMOS
8-bit analog-to-digital converter with a high-speed serial in-
terface. Unlike the conventional practice of specifying per-
formance at a single sample rate only, the ADC081S051 is
fully specified over a sample rate range of 200 kSPS to 500
kSPS. The converter is based on a successive-
approximation register architecture with an internal track-
and-hold circuit.
The output serial data is straight binary, and is compatible
with several standards, such as SPI, QSPI,
MICROWIRE, and many common DSP serial interfaces.
The ADC081S051 operates with a single supply that can
range from +2.7V to +5.25V. Normal power consumption
using a +3V or +5V supply is 2.9 mW and 10.5 mW, respec-
tively. The power-down feature reduces the power consump-
tion to as low as 2.6 µW using a +5V supply.
The ADC081S051 is packaged in an 6-lead LLP package.
Operation over the industrial temperature range of −40˚C to
+85˚C is guaranteed.
Features
n Specified over a range of sample rates.
n 6-lead LLP package
n Variable power management
n Single power supply with 2.7V - 5.25V range
n SPI/QSPI/MICROWIRE/DSP compatible
Key Specifications
n DNL
n INL
n SNR
n Power Consumption
— 3V Supply
— 5V Supply
+ 0.07 / −0.06 LSB (typ)
+ 0.06 / −0.07 LSB (typ)
49.6 dB (typ)
2.9 mW (typ)
10.5 mW (typ)
Applications
n Portable Systems
n Remote Data Aquisitions
n Instrumentation and Control Systems
Pin-Compatible Alternatives by Resolution and Speed
All devices are fully pin and function compatible.
Resolution
Specified for Sample Rate Range of:
50 to 200 kSPS
200 to 500 kSPS
500 kSPS to 1 MSPS
12-bit
ADC121S021
ADC121S051
ADC121S101
10-bit
ADC101S021
ADC101S051
ADC081S101
8-bit
ADC081S021
ADC081S051
ADC081S101
Connection Diagram
Ordering Information
Order Code
ADC081S051CISD
ADC081S051CISDX
Temperature Range
−40˚C to +85˚C
−40˚C to +85˚C
20145505
Description
6-Lead LLP Package
6-Lead LLP Package, Tape & Reel
Top Mark
X6C
X6C
TRI-STATE® is a trademark of National Semiconductor Corporation
QSPIand SPIare trademarks of Motorola, Inc.
© 2005 National Semiconductor Corporation DS201455
www.national.com
Free Datasheet http://www.datasheet4u.com/




ADC081S051 pdf, 반도체, 판매, 대치품
ADC081S051 Converter Electrical Characteristics (Note 9) (Continued)
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 4 MHz to 10 MHz,
fSAMPLE = 200 kSPS to 500 kSPS, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA =
25˚C.
Symbol
Parameter
Conditions
Typical
Limits
(Note 9)
Units
ANALOG INPUT CHARACTERISTICS
VIN
IDCL
CINA
Input Range
DC Leakage Current
Input Capacitance
Track Mode
Hold Mode
0 to VA
30
4
±1
V
µA (max)
pF
pF
DIGITAL INPUT CHARACTERISTICS
VIH Input High Voltage
VIL Input Low Voltage
IIN Input Current
CIND
Digital Input Capacitance
DIGITAL OUTPUT CHARACTERISTICS
VA = +5.25V
VA = +5.25V
VA = +3.6V
VIN = 0V or VA
2.4 V (min)
0.8 V (max)
0.4 V (max)
±0.1 ±1 µA (max)
2 4 pF (max)
VOH
VOL
IOZH,
IOZL
COUT
Output High Voltage
Output Low Voltage
TRI-STATE® Leakage Current
TRI-STATE® Output Capacitance
Output Coding
ISOURCE = 200 µA
ISOURCE = 1 mA
ISINK = 200 µA
ISINK = 1 mA
VA − 0.03
VA − 0.1
0.03
0.1
VA − 0.2
0.4
V (min)
V
V (max)
V
±0.1 ±10 µA (max)
2 4 pF (max)
Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS (CL = 10 pF)
VA Supply Voltage
2.7
5.25
V (min)
V (max)
Supply Current, Normal Mode
(Operational, CS low)
IA
Supply Current, Shutdown (CS high)
Power Consumption, Normal Mode
(Operational, CS low)
PD Power Consumption, Shutdown (CS
high)
AC ELECTRICAL CHARACTERISTICS
VA = +5.25V,
fSAMPLE = 200 kSPS
VA = +3.6V,
fSAMPLE = 200 kSPS
fSCLK= 0 MHz, VA = +5.25V
fSAMPLE = 0 kSPS
VA = +5.25V, fSCLK = 10MHz,
fSAMPLE = 0 kSPS
VA = +5.25V
VA = +3.6V
fSCLK = 0 MHz, VA = +5.25V
fSAMPLE = 0 kSPS
VA = +5.25V, fSCLK = 10 MHz,
fSAMPLE = 0 kSPS
2.0
0.8
0.5
22
10.5
2.9
2.6
0.12
2.4
1.0
12.6
3.6
mA (max)
mA (max)
µA
µA
mW (max)
mW (max)
µW
mW
fSCLK
Clock Frequency
(Note 8)
4 MHz (min)
10 MHz (max)
fS Sample Rate
(Note 8)
50 200 kSPS (min)
500 kSPS (max)
tCONV
DC
Conversion Time
SCLK Duty Cycle
fSCLK = 10 MHz
16 SCLK cycles
40 % (min)
50
60 % (max)
tACQ
Track/Hold Acquisition Time
Throughput Time
Acquisition Time + Conversion Time
400 ns (max)
20 SCLK cycles
www.national.com
4
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ADC081S051 전자부품, 판매, 대치품
Specification Definitions
ACQUISITION TIME is the time required to acquire the input
voltage. That is, it is time required for the hold capacitor to
charge up to the input voltage.
APERTURE DELAY is the time between the fourth falling
SCLK edge of a conversion and the time when the input
signal is acquired or held for conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
CONVERSION TIME is the time required, after the input
voltage is acquired, for the ADC to convert the input voltage
to a digital word.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital
waveform is high to the total time of one period. The speci-
fication here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as
(SINAD − 1.76) / 6.02 and says that the converter is equiva-
lent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation of the last code transition
(111...110) to (111...111) from the ideal (VREF − 1.5 LSB),
after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from
negative full scale (12 LSB below the first code transition)
through positive full scale (12 LSB above the last code
transition). The deviation of any given code from this straight
line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the second and third
order intermodulation products to the sum of the power in
both of the original frequencies. IMD is usually expressed in
dB.
MISSING CODES are those output codes that will never
appear at the ADC outputs. The ADC081S051 is guaranteed
not to have any missing codes.
OFFSET ERROR is the deviation of the first code transition
(000...000) to (000...001) from the ideal (i.e. GND + 0.5
LSB).
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
Is the ratio, expressed in dB, of the rms value of the input
signal to the rms value of all of the other spectral compo-
nents below half the clock frequency, including harmonics
but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal and the peak spurious signal where a spurious signal
is any signal present in the output spectrum that is not
present at the input, excluding d.c.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB or dBc, of the rms total of the first five
harmonic components at the output to the rms level of the
input signal frequency as seen at the output. THD is calcu-
lated as
where Af1 is the RMS power of the input frequency at the
output and Af2 through Af6 are the RMS power in the first 5
harmonic frequencies.
THROUGHPUT TIME is the minimum time required between
the start of two successive conversion. It is the acquisition
time plus the conversion time.
TOTAL UNADJUSTED ERROR is the worst deviation found
from the ideal transfer function. As such, it is a comprehen-
sive specification which includes full scale error, linearity
error, and offset error.
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