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PDF AT90USB647 Data sheet ( Hoja de datos )
| Número de pieza | AT90USB647 | |
| Descripción | (AT90USBxxx) 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 135 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier
• Non-volatile Program and Data Memories
– 32/64/128K Bytes of In-System Self-Programmable Flash
• Endurance: 100,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
• USB Bootloader programmed by default in the Factory
• In-System Programming by On-chip Boot Program hardware activated after
reset
• True Read-While-Write Operation
• All supplied parts are preprogramed with a default USB bootloader
– 1K/2K/4K (32K/64K/128K Flash version) Bytes EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 2.5K/4K/8K (32K/64K/128K Flash version) Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• USB 2.0 Full-speed/Low-speed Device and On-The-Go Module
– Complies fully with:
– Universal Serial Bus Specification REV 2.0
– On-The-Go Supplement to the USB 2.0 Specification Rev 1.0
– Supports data transfer rates up to 12 Mbit/s and 1.5 Mbit/s
• USB Full-speed/Low Speed Device Module with Interrupt on Transfer Completion
– Endpoint 0 for Control Transfers : up to 64-bytes
– 6 Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or
Isochronous Transfers
– Configurable Endpoints size up to 256 bytes in double bank mode
– Fully independant 832 bytes USB DPRAM for endpoint memory allocation
– Suspend/Resume Interrupts
– Power-on Reset and USB Bus Reset
– 48 MHz PLL for Full-speed Bus Operation
– USB Bus Disconnection on Microcontroller Request
• USB OTG Reduced Host :
– Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
for OTG dual-role devices
– Provide Status and control signals for software implementation of HNP and SRP
– Provides programmable times required for HNP and SRP
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– Two16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode
8-bit
Microcontroller
with
64/128K Bytes
of ISP Flash
and USB
Controller
ATmega32U6
AT90USB646
AT90USB647
AT90USB1286
AT90USB1287
7593H–AVR–11/08
Free Datasheet http://www.datasheet4u.com/
1 page  
ATmega32U6/AT90USB64/128
ATmega32U6/AT90USB64/128 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
PF7 - PF0
PA7 - P A0
PC7 - PC0
VCC
GND
POR TF DRIVERS
DATA REGISTER
PORT F
DATA DIR.
REG. PORT F
POR TA DRIVERS
POR TC DRIVERS
DATA REGISTER
PORT A
DATA DIR.
REG. PORT A
DATA REGISTER
PORT C
8-BIT DA TA BUS
DATA DIR.
REG. PORT C
AVCC
AGND
AREF
JTAG TAP
ON-CHIP DEBUG
BOUNDARY-
SCAN
PROGRAMMING
LOGIC
ADC
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
POR - BOD
RESET
ST ACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
ST ATUS
REGISTER
INTERNAL
OSCILLA TOR
W ATCHDOG
TIMER
MCU CONTROL
REGISTER
TIMER/
COUNTERS
INTERRUPT
UNIT
EEPROM
CALIB. OSC
OSCILLA TOR
TIMING AND
CONTROL
PLL
USART1
SPI
USB
TWO-WIRE SERIAL
INTERFACE
DATA REGISTER
PORTE
DATA DIR.
REG. PORTE
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
POR TE DRIVERS
POR TB DRIVERS
POR TD DRIVERS
7593H–AVR–11/08
PE7 - PE0
PB7 - PB0
PD7 - PD0
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
ATmega32U6/AT90USB64/128
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic opera-
tion, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word for-
mat. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the
Application Program section. Both sections have dedicated Lock bits for write and read/write
protection. The SPM instruction that writes into the Application Flash memory section must
reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-
tion. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F. In addition, the
ATmega32U6/AT90USB64/128 has Extended I/O space from 0x60 - 0xFF in SRAM where only
the ST/STS/STD and LD/LDS/LDD instructions can be used.
4.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
7593H–AVR–11/08
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT90USB647.PDF ] | |
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