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PDF ADM1060 Data sheet ( Hoja de datos )
| Número de pieza | ADM1060 | |
| Descripción | Communications System Supervisory/Sequencing Circuit | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Communications System
Supervisory/Sequencing Circuit
ADM1060
FEATURES
Faults detected on 7 independent supplies
1 high voltage supply (2 V to 14.4 V)
4 positive voltage only supplies (2 V to 6 V)
2 positive/negative voltage supplies
(+2 V to +6 V and –2 V to –6 V)
Watchdog detector input—timeout delay programmable
from 200 ms to 12.8 sec
4 general-purpose logic inputs
Programmable logic block—combinatorial and sequencing
logic control of all inputs and outputs
9 programmable output drivers:
Open collector (external resistor required)
Open collector with internal pull-up to VDD
Fast internal pull-up to VDD
Open collector with internal pull-up to VPn
Fast internal pull-up to VPn
Internally charge-pumped high drive (for use with
external N-channel FETs—PDOs 1 to 4 only)
EEPROM—256 bytes of user EEPROM
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VPn, VH = 1 V
APPLICATIONS
Central office systems
Servers
Infrastructure network boards
High density, multivoltage system cards
GENERAL DESCRIPTION
The ADM1060 is a programmable supervisory/sequencing
device that offers a single chip solution for multiple power
supply fault detection and sequencing in communications
systems.
In central offices, servers, and other infrastructure systems, a
common backplane dc supply is reduced to multiple board sup-
plies using dc-to-dc converters. These multiple supplies are used
to power different sections of the board, such as 3.3 V logic
circuits, 5 V logic circuits, DSP core, and DSP I/O circuits. There
is usually a requirement that certain sections power up before
others; for example, a DSP core may need to power up before
the DSP I/O, or vice versa, to avoid damage, miscommunication,
or latch-up. The ADM1060 facilitates this, providing supply
fault detection and sequencing/combinatorial logic for up to
seven independent supplies. The seven supply fault detectors
consist of one high voltage detector (up to +14.4 V), two bipolar
voltage detectors (up to +6 V or down to −6 V), and four posi-
tive low voltage detectors (up to +6 V). All of the detectors can
be programmed to detect undervoltage, overvoltage, or out-of-
window (undervoltage or overvoltage) conditions. The inputs to
these supply fault detectors are via the VH (high voltage) pin,
VBn (positive or negative) pins, and VPn (positive only) pins.
Either the VH supply or one of the VPn supplies is used to
power the ADM1060 (whichever is highest). This ensures that
in the event of a supply failure, the ADM1060 is kept alive for as
long as possible, thus enabling a reliable fault flag to be asserted
and the system to be powered down in an ordered fashion.
Other inputs to the ADM1060 include a watchdog detector
(WDI) and four general-purpose inputs (GPIn). The watchdog
detector can be used to monitor a processor clock. If the clock
does not toggle (transition from low to high or from high to
low) within a programmable timeout period (up to 18 sec.), a
fail flag will assert. The four general-purpose inputs can be con-
figured as logic buffers or to detect positive/negative edges and
to generate a logic pulse or level from those edges. Thus, the
user can input control signals from other parts of the system
(e.g., RESET or POWER_GOOD) to gate the sequencing of the
supplies supervised by the ADM1060.
The ADM1060 features nine programmable driver outputs
(PDOs). All nine outputs can be configured to be logic outputs,
which can provide multiple functions for the end user such as
RESET generation, POWER_GOOD status, enabling of LDOs,
and watchdog timeout assertion. PDOs 1 to 4 have the added
feature of being able to provide an internally charge-pumped
high voltage for use as the gate drive of an external N-channel
FET that could be placed in the path of one of the supplies
being supervised.
(continued on Page 3)
.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
ADM1060
ADM1060
VH 8
VP1 9
VP2 10
VP3 11
VP4 12
VB1 13
VB2 14
GPI1 28
GPI2 27
GPI3 26
GPI4 25
WDI 24
HIGH SUPPLY
(14.4V)
FAULT DETECTOR
POSITIVE
SUPPLY FAULT
DETECTOR 1
POSITIVE
SUPPLY FAULT
DETECTOR 4
BIPOLAR
SUPPLY FAULT
DETECTOR 1
BIPOLAR
SUPPLY FAULT
DETECTOR 2
INPUT LOGIC
SIGNAL
CONDITION
WATCHDOG
FAULT
DETECTOR
PROGRAMMABLE
LOGIC BLOCK
ARRAY
(PLBA)
PLB
MACROCELL 1
PLB
MACROCELL 2
PLB
MACROCELL 3
PLB
MACROCELL 4
PLB
MACROCELL 5
PLB
MACROCELL 6
PLB
MACROCELL 7
PLB
MACROCELL 8
PLB
MACROCELL 9
GND 6
VCCP 7
VREF
INTERNAL
5.25V SUPPLY
REGULATED
5.25V SUPPLY
CHARGE PUMP
PROGRAMMABLE
DELAY BLOCKS
PDB1
tRISE tFALL
PDB2
tRISE tFALL
PDB3
tRISE tFALL
PDB4
tRISE tFALL
PDB5
tRISE tFALL
PDB6
tRISE tFALL
PDB7
tRISE tFALL
PDB8
tRISE tFALL
PDB9
tRISE tFALL
DATA, ADDRESS, AND
WRITE ENABLE BUSES
TO STORE CONTROL
INFORMATION LOCAL
TO FUNCTIONS
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
15 PDO1
16 PDO2
17 PDO3
18 PDO4
19 PDO5
20 PDO6
21 PDO7
22 PDO8
23 PDO9
SMBus DATA
100kHz CLOCK
VDD
ARBITRATOR
SMBus INTERFACE
DEVICE
CONTROLLER
EEPROM
5 4321
Figure 1. Functional Block Diagram
Rev. B | Page 4 of 52
5 Page 
ADM1060
110
108
106
104
102
100
98
96
94
92
90
–40 –25 –10
5 20 35 50
TEMPERATURE (°C)
65
Figure 14. Oscillator Frequency vs. Temperature
80
6.00
5.75
5.50
5.25
5.00
4.75
4.50
0
VVDDCAP = 4.75V
VVDDCAP = 2.7V
100 200 300
ILOAD (µA)
Figure 15. VCCP vs. Load Current
400
500
3.0
2.5
2.0
VVDDCAP = 2.7V
1.5
1.0
VVDDCAP = 4.75V
0.5
0
–40 –25 –10
5 20 35 50
TEMPERATURE (°C)
65
Figure 16. GPI Threshold vs. Temperature
80
Rev. B | Page 10 of 52
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADM1060.PDF ] | |
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