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PE83336 데이터시트 PDF




Peregrine Semiconductor에서 제조한 전자 부품 PE83336은 전자 산업 및 응용 분야에서
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부품번호 PE83336 기능
기능 3.0 GHz Integer-N PLL
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PE83336 데이터시트, 핀배열, 회로
Product Description
Peregrine’s PE83336 is a high performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The
superior phase noise performance of the PE83336 makes
it ideal for rugged military environments including: radio
handsets, radar, avionics, missiles, etc.
The PE83336 features a 10/11 dual modulus prescaler,
counters and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial
or parallel interface and can also be directly hard wired.
Fabricated in Peregrine’s patented UTSi® (Ultra Thin
Silicon) CMOS technology, the PE83336, while optimized
for stringent military environments, offers excellent RF
performance together with the economy and integration of
conventional CMOS.
PRODUCT SPECIFICATION
PE83336
Military Operating Temperature Range
3.0 GHz Integer-N PLL for Low
Phase Noise Applications
Features
3.0 GHz operation
÷10/11 dual modulus prescaler
Internal phase detector
Serial, parallel or hardwired
programmable
Ultra-low phase noise
Available in 44-lead CQFJ
Figure 1. Block Diagram
Fin Prescaler
Fin 10 / 11
D(7:0)
8
Sdata
Primary
20-bit
Latch 20
Pre_en
M(6:0)
A(3:0)
R(3:0)
fr
Secon-
dary
20-bit
Latch
20
20
20
16
Main
Counter
13
66
R Counter
fp
Phase
Detector
PD_U
PD_D
fc
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
Page 1 of 14
Free Datasheet http://www.datasheet4u.com/




PE83336 pdf, 반도체, 판매, 대치품
PE83336
Product Specification
Pin No.
(44-lead
CQFJ)
Pin
Name
Interface
Mode
Type
Description
30 fp
ALL
31
VDD-fp
ALL
32
Dout
Serial,
Parallel
Output
(Note 1)
Output
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 31.
VDD for fp. Can be left floating or connected to GND to disable the fp output.
Data Out. The MSEL signal and the raw prescaler output are available on Dout through
enhancement register programming.
33 VDD
ALL
34 Cext ALL
(Note 1)
Output
Same as pin 1.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kseries resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting
amplifier used for driving LD.
35 VDD
ALL
36
PD_D
ALL
37
PD_U
ALL
38
VDD-fc
ALL
39 fc
ALL
40 GND ALL
(Note 1)
Output
(Note 1)
Output
Same as pin 1.
PD_D is pulse down when fp leads fc.
PD_U is pulse down when fc leads fp.
VDD for fc can be left floating or connected to GND to disable the fc output.
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 38.
Ground.
41 GND ALL
Ground.
42 fr
43 LD
ALL
ALL
Input
Output
Reference frequency input.
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high
impedance, otherwise LD is a logic low (“0”).
44 Enh
Serial,
Parallel
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
N/A NC
ALL
No connection.
Note 1:
All VDD pins are connected by diodes and must be supplied with the same positive voltage level.
VDD-fp and VDD-fp are used to power the fp and fc outputs and can alternatively be left floating or connected to GND to disable the fp and fc
outputs.
Note 2: All digital input pins have 70 kpull-down resistors to ground.
Copyright Peregrine Semiconductor Corp. 2003
Page 4 of 14
File No. 70/0137~01A
|
UTSi CMOS RFIC SOLUTIONS
Free Datasheet http://www.datasheet4u.com/

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PE83336 전자부품, 판매, 대치품
PE83336
Product Specification
Table 6. AC Characteristics
VDD = 3.0 V, -55° C TA 125° C, unless otherwise specified
Symbol
Parameter
Conditions
Min Typ
Max Units
Control Interface and Latches (see Figures 3, 4, 5)
fClk Serial data clock frequency
tClkH Serial clock HIGH time
tClkL Serial clock LOW time
tDSU Sdata set-up time after Sclk rising edge, D[7:0] set-up
time to M1_WR, M2_WR, A_WR, E_WR rising edge
tDHLD
Sdata hold time after Sclk rising edge, D[7:0] hold time to
M1_WR, M2_WR, A_WR, E_WR rising edge
tPW S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
tCWR Sclk rising edge to S_WR rising edge. S_WR, M1_WR,
M2_WR, A_WR falling edge to Hop_WR rising edge
tCE Sclk falling edge to E_WR transition
tWRC S_WR falling edge to Sclk rising edge. Hop_WR falling
edge to S_WR, M1_WR, M2_WR, A_WR rising edge
tEC E_WR transition to Sclk rising edge
tMDO MSEL data out delay after Fin rising edge
Main Divider (Including Prescaler)
CL = 12 pf
Fin Operating frequency
PFin Input level range
External AC coupling
External AC coupling
85°C < TA 125°C
Main Divider (Prescaler Bypassed)
Fin Operating frequency
PFin Input level range
External AC coupling
External AC coupling
85°C < TA 125°C
Reference Divider
fr Operating frequency
Pfr Reference input power
Vfr Input sensitivity
(Note 1)
Single ended input
External AC coupling
(Note 3)
Phase Detector
fc Comparison frequency
(Note 1)
SSB Phase Noise : Output Referred (Fin = 1918MHz, fr = 10 MHz, fc = 1MHz, LBW = 70 kHz)
PNOR
Output Referred Phase Noise
100 Hz Offset: VDD
= 3.0V, T = 25ºC
PNOR
Output Referred Phase Noise
1000 Hz Offset: VDD
= 3.0V, T = 25ºC
30
30
10
10
30
30
30
30
30
500
-5
0
50
-5
0
(Note 2)
-2
0.5
-78
-94
10
8 (Note 5)
3000
5
5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
dBm
dBm
300 MHz
5 dBm
5 dBm
100 MHz
10 dBm
VP-P
20
(Note 4)
(Note 4)
MHz
dBc/Hz
dBc/Hz
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Parameter is guaranteed through characterization only and is not tested.
Running at low frequencies (< 10 MHz sinewave), the device will still be functional but may cause phase noise degradation. Inserting a low-
noise amplifier to square up the edges is recommended at lower input frequencies.
CMOS logic levels may be used if DC coupled. For optimum phase noise performance, the reference input falling edge rate should be faster
than 80mV/ns.
All devices are screened to phase noise limits listed in Table 7. The magnitude of the tester uncertainty precludes testing phase noise as part
of qualification testing. These parameters are also exempt from PDA requirements.
Parameter is tested using 100pF load capacitance and is guaranteed through characterization only. Typical test delay is 12nS.
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
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부품번호상세설명 및 기능제조사
PE83336

3.0 GHz Integer-N PLL

Peregrine Semiconductor
Peregrine Semiconductor

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