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CAT93C66 데이터시트 PDF




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부품번호 CAT93C66 기능
기능 4 kb Microwire Serial CMOSEEPROM
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CAT93C66 데이터시트, 핀배열, 회로
CAT93C66, CAT93W66
4 kb Microwire Serial CMOS
EEPROM
Description
The CAT93C66 is a 4 kb CMOS Serial EEPROM device which is
organized as either 256 registers of 16 bits (ORG pin at VCC) or 512
registers of 8 bits (ORG pin at GND). The CAT93W66 features x16
memory organization only. Each register can be written (or read)
serially by using the DI (or DO) pin. The device features sequential
read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
Features
High Speed Operation: 2 MHz
1.8 V to 5.5 V Supply Voltage Range
Selectable x8 or x16 Memory Organization: CAT93C66
Sequential Read
Software Write Protection
Power−up Inadvertent Write Protection
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Ranges
8−lead PDIP, SOIC, TSSOP and 8−pad TDFN Packages
These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
VCC
VCC
ORG
CS
SK
DI
CAT93C66
CS
DO SK
DI
CAT93W66
DO
GND
GND
Figure 1. Functional Symbols
CAT93C66 Selectable Organization:
When the ORG pin is connected to VCC, the x16 organization is
selected. When it is connected to ground, the x8 organization is
selected. If the ORG pin is left unconnected, then an internal pull−up
device will select the x16 organization.
CAT93W66*:
The device works in x16 mode only.
*Not recommended for new designs
www.onsemi.com
SOIC−8
V SUFFIX
CASE 751BD
TDFN−8
VP2 SUFFIX
CASE 511AK
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
SOIC−8
X SUFFIX
CASE 751BE
PIN CONFIGURATION
(Top View)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
PDIP (L), SOIC (V, X),
TSSOP (Y),
TDFN (VP2)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 NC
5 GND
TDFN (VP2)
CAT93W66*
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
August, 2015 − Rev. 13
1
Publication Order Number:
CAT93C66/D




CAT93C66 pdf, 반도체, 판매, 대치품
CAT93C66, CAT93W66
Table 8. A.C. TEST CONDITIONS
Input Rise and Fall Times
50 ns
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
0.4 V to 2.4 V
0.8 V, 2.0 V
0.2 VCC to 0.7 VCC
0.5 VCC
4.5 V VCC 5.5 V
4.5 V VCC 5.5 V
1.8 V VCC 4.5 V
1.8 V VCC 4.5 V
Output Load
Current Source IOLmax/IOHmax; CL = 100 pF
Device Operation
The CAT93C66 is a 4096−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C66 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 11−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
12−bit instructions control the reading, writing and erase
operations of the device. The CAT93W66 works in x16
mode only. The device operates on a single power supply
and will generate on chip, the high voltage required during
any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation. The serial communication protocol
follows the timing shown in Figure 2.
The ready/busy status can be determined after the start of
internal write cycle by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 8−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
The instruction format is shown in Instruction Set table.
Table 9. INSTRUCTION SET
Address
Instruction
READ
Start Bit
1
Opcode
10
x8 (Note 10)
A8−A0
x16
A7−A0
ERASE
1
11
A8−A0
A7−A0
WRITE
1
01 A8−A0
A7−A0
EWEN
1
00
11XXXXXXX
11XXXXXX
EWDS
1
00
00XXXXXXX
00XXXXXX
ERAL
1
00
10XXXXXXX
10XXXXXX
WRAL
1
00
01XXXXXXX
01XXXXXX
10. The x8 memory organization is available for the CAT93C66 only.
Data
x8 (Note 10)
x16
D7−D0
D15−D0
D7−D0
D15−D0
Comments
Read Address AN – A0
Clear Address AN – A0
Write Address AN – A0
Write Enable
Write Disable
Clear All Addresses
Write All Addresses
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CAT93C66 전자부품, 판매, 대치품
CAT93C66, CAT93W66
Erase All
Upon receiving an ERAL command (Figure 7), the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
device can be determined by selecting the device and polling
the DO pin. Once cleared, the contents of all memory bits
return to a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN (Figure 8). The falling edge of CS will start the self
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy status of
the device can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
SK
CS
STATUS VERIFY
STANDBY
DI
1
00
10
tCS
HIGH−Z
DO
tSV
BUSY READY
tEW
tHZ
HIGH−Z
Figure 7. ERAL Instruction Timing
SK
CS STATUS VERIFY STANDBY
tCSMIN
DI 1 0 0 0 1
DN D0
tSV tHZ
DO BUSY READY
HIGH−Z
tEW
Figure 8. WRAL Instruction Timing
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