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부품번호 | CAV25080 기능 |
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기능 | (CAV25080 / CAV25160) SPI Serial CMOS EEPROM | ||
제조업체 | ON Semiconductor | ||
로고 | |||
전체 13 페이지수
CAV25080, CAV25160
8-Kb and 16-Kb SPI Serial
CMOS EEPROM
Description
The CAV25080/25160 are 8−Kb/16−Kb Serial CMOS EEPROM
devices internally organized as 1024x8/2048x8 bits. They feature a
32−byte page write buffer and support the Serial Peripheral Interface
(SPI) protocol. The device is enabled through a Chip Select (CS)
input. In addition, the required bus signals are a clock input (SCK),
data input (SI) and data output (SO) lines. The HOLD input may be
used to pause any serial communication with the CAV25080/25160
device. These devices feature software and hardware write protection,
including partial as well as full array protection.
Features
• Automotive Temperature Grade 1 (−40°C to +125°C)
• 10 MHz SPI Compatible
• 2.5 V to 5.5 V Supply Voltage Range
• SPI Modes (0,0) & (1,1)
• 32−byte Page Write Buffer
• Self−timed Write Cycle
• Hardware and Software Protection
• Block Write Protection
− Protect 1/4, 1/2 or Entire EEPROM Array
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial and Extended Temperature Range
• 8−lead SOIC and TSSOP Packages
• These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
VCC
SI
CS
WP
HOLD
SCK
CAV25080
CAV25160
SO
VSS
Figure 1. Functional Symbol
http://onsemi.com
SOIC−8
V SUFFIX
CASE 751BD
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATION
CS 1
SO
VCC
HOLD
WP SCK
VSS SI
SOIC (V), TSSOP (Y)
Pin Name
CS
SO
WP
VSS
SI
SCK
HOLD
VCC
PIN FUNCTION
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
November, 2011 − Rev. 0
1
Publication Order Number:
CAV25080/D
Free Datasheet http://www.datasheet4u.com/
CAV25080, CAV25160
Pin Description
SI: The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAV25080/160.
CS: The chip select input pin is used to enable/disable the
CAV25080/160. When CS is high, the SO output is tri−stated
(high impedance) and the device is in Standby Mode (unless
an internal write operation is in progress). Every
communication session between host and CAV25080/160
must be preceded by a high to low transition and concluded
with a low to high transition of the CS input.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
HOLD: The HOLD input pin is used to pause transmission
between host and CAV25080/160, without having to
retransmit the entire sequence at a later time. To pause,
HOLD must be taken low and to resume it must be taken
back high, with the SCK input low during both transitions.
CS
When not used for pausing, the HOLD input should be tied
to VCC, either directly or through a resistor.
Functional Description
The CAV25080/160 devices support the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8−bit instruction register. The instruction
set and associated op−codes are listed in Table 7.
Reading data stored in the CAV25080/160 is
accomplished by simply providing the READ command and
an address. Writing to the CAV25080/160, in addition to a
WRITE command, address and data, also requires enabling
the device for writing by first setting certain bits in a Status
Register, as will be explained later.
After a high to low transition on the CS input pin, the
CAV25080/160 will accept any one of the six instruction
op−codes listed in Table 7 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
Table 7. INSTRUCTION SET
Instruction
Opcode
WREN
0000 0110
WRDI
0000 0100
RDSR
0000 0101
WRSR
0000 0001
READ
0000 0011
WRITE
0000 0010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
tCS
tCNH
tCSS
tWH
tWL
tCSH
tCNS
SCK
tSU tH
tRI
tFI
SI
VALID
IN
HI−Z
SO
tV
tHO
VALID
OUT
tV
tDIS
HI−Z
Figure 2. Synchronous Data Timing
Status Register
The Status Register, as shown in Table 8, contains a
number of status and control bits.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 9. The protected
blocks then become read−only.
http://onsemi.com
4
Free Datasheet http://www.datasheet4u.com/
4페이지 CAV25080, CAV25160
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16−bit address
and data as shown in Figure 5. Only 10 significant address
bits are used by the CAV25080 and 11 by the CAV25160.
The rest are don’t care bits, as shown in Table 11. Internal
programming will start after the low to high CS transition.
During an internal write cycle, all commands, except for
RDSR (Read Status Register) will be ignored. The RDY bit
will indicate if the internal write cycle is in progress (RDY
high), or the device is ready to accept commands (RDY
low).
Table 11. BYTE ADDRESS
Device
CAV25080
CAV25160
Address Significant Bits
A9 − A0
A10 − A0
Page Write
After sending the first data byte to the CAV25080/160, the
host may continue sending data, up to a total of 32 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the
CAV25080/160 is automatically returned to the write
disable state.
Address Don’t Care Bits
A15 − A10
A15 − A11
# Address Clock Pulse
16
16
CS
SCK
SI
012345678
21 22 23 24 25 26 27 28 29 30 31
00
OPCODE
00 0 01
BYTE ADDRESS*
DATA IN
0 AN
A0 D7 D6 D5 D4 D3 D2 D1 D0
SO HIGH IMPEDANCE
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 11)
Figure 5. Byte WRITE Timing
CS
SCK
012345678
21 22 23 24−31 32−39 24+(N−1)x8−1 .. 24+(N−1)x8
24+Nx8−1
OPCODE
BYTE ADDRESS*
DATA IN
Data Byte N
SI 0 0 0 0 0 0 1 0 AN
A0 7..1 0
Data Data Data
Byte 1 Byte 2 Byte 3
SO HIGH IMPEDANCE
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 11)
Figure 6. Page WRITE Timing
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7
Free Datasheet http://www.datasheet4u.com/
7페이지 | |||
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CAV25080 | (CAV25080 / CAV25160) SPI Serial CMOS EEPROM | ON Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |