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NVMD4N03 데이터시트 PDF




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기능 Power MOSFET ( Transistor )
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NVMD4N03 데이터시트, 핀배열, 회로
NTMD4N03, NVMD4N03
Power MOSFET
4 A, 30 V, NChannel SO8 Dual
Features
Designed for use in low voltage, high speed switching applications
Ultra Low OnResistance Provides
Higher Efficiency and Extends Battery Life
RDS(on) = 0.048 W, VGS = 10 V (Typ)
RDS(on) = 0.065 W, VGS = 4.5 V (Typ)
Miniature SO8 Surface Mount Package Saves Board Space
Diode is Characterized for Use in Bridge Circuits
Diode Exhibits High Speed, with Soft Recovery
NVMD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ101
Qualified and PPAP Capable*
These Devices are PbFree and are RoHS Compliant
Applications
DCDC Converters
Computers
Printers
Cellular and Cordless Phones
Disk Drives and Tape Drives
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value
DraintoSource Voltage
GatetoSource Voltage Continuous
Drain Current
Continuous @ TA = 25°C
Single Pulse (tp 10 ms)
Total Power Dissipation
@ TA = 25°C (Note 1)
Operating and Storage
Temperature Range
VDSS
VGS
ID
IDM
PD
TJ, Tstg
30
"20
4.0
12
2.0
55 to
+150
Unit
V
V
Adc
Apk
W
°C
Single Pulse DraintoSource
Avalanche Energy Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc,
Peak IL = 4.45 Apk, L = 8 mH,
RG = 25 W)
Thermal Resistance
JunctiontoAmbient (Note 1)
EAS
RqJA
80 mJ
62.5 °C/W
Maximum Lead Temperature for
Soldering Purposes for 10 seconds
TL 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 1pad size, t 10 s
http://onsemi.com
VDSS
30 V
RDS(ON) Typ
48 mW @ VGS = 10 V
ID Max
4.0 A
NChannel
DD
GG
SS
8
1
SOIC8
SUFFIX NB
CASE 751
STYLE 11
MARKING DIAGRAM*
AND PIN ASSIGNMENT
D1 D1 D2 D2
8
E4N03
AYWW G
G
1
S1 G1 S2 G2
E4N03 = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
NTMD4N03R2G
NVMD4N03R2G*
Package
SOIC8
(PbFree)
SOIC8
(PbFree)
Shipping
2500 / Tape &
Reel
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
© Semiconductor Components Industries, LLC, 2013
August, 2013 Rev. 4
1
Publication Order Number:
NTMD4N03R2/D
Free Datasheet http://www.datasheet4u.com/




NVMD4N03 pdf, 반도체, 판매, 대치품
NTMD4N03, NVMD4N03
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because draingate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when
calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
800
Ciss
600 Crss
TJ = 25°C
400
Ciss
200
0
10
Coss
VDS = 0 V VGS = 0 V
Crss
5 0 5 10 15 20
VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE
VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
25
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NVMD4N03 전자부품, 판매, 대치품
NTMD4N03, NVMD4N03
TYPICAL ELECTRICAL CHARACTERISTICS
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
0.001
1.0E-05
1.0E-04
0.0106 W 0.0431 W 0.1643 W 0.3507 W 0.4302 W
CHIP
JUNCTION 0.0253 F 0.1406 F 0.5064 F 2.9468 F 177.14 F
AMBIENT
1.0E-03
1.0E-02
1.0E-01
1.0E+00
t, TIME (s)
Figure 13. Thermal Response
1.0E+01
1.0E+02
1.0E+03
IS
tp
di/dt
trr
ta tb
0.25 IS
IS
TIME
Figure 14. Diode Reverse Recovery Waveform
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NVMD4N03

Power MOSFET ( Transistor )

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