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33904 PDF 데이터시트 ( Data , Function )

부품번호 33904 기능
기능 (33903 - 33905) SBC Gen2
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33904 데이터시트, 핀배열, 회로
Freescale Semiconductor
Technical Data
SBC Gen2 with CAN High Speed
and LIN Interface
The 33903/4/5 is the second generation family of the System Basis
Chip (SBC). It combines several features and enhances present
module designs. The device works as an advanced power
management unit for the MCU with additional integrated circuits such
as sensors and CAN transceivers. It has a built-in enhanced high-speed
CAN interface (ISO11898-2 and -5) with local and bus failure
diagnostics, protection, and fail-safe operation modes. The SBC may
include zero, one or two LIN 2.1 interfaces with LIN output pin switches.
It includes up to four wake-up input pins that can also be configured as
output drivers for flexibility.
This device implements multiple Low-power (LP) modes, with very
low-current consumption. In addition, the device is part of a family
concept where pin compatibility adds versatility to module design.
The 33903/4/5 also implements an innovative and advanced fail-safe
state machine and concept solution.
Features
• Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with
possibility of usage external PNP to extend current capability and
share power dissipation
• Voltage, current, and temperature protection
• Extremely low quiescent current in LP modes
• Fully-protected embedded 5.0 V regulator for the CAN driver
• Multiple under-voltage detections to address various MCU
specifications and system operation modes (i.e. cranking)
• Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs,
with over-current detection and under-voltage protection
• MUX output pin for device internal analog signal monitoring and
power supply monitoring
• Advanced SPI, MCU, ECU power supply, and critical pins
diagnostics and monitoring.
• Multiple wake-up sources in LP modes: CAN or LIN bus,
I/O transition, automatic timer, SPI message, and VDD over-current
detection.
• ISO11898-5 high-speed CAN interface compatibility for baud rates of
40 kb/s to 1.0 Mb/s
• Scalable product family of devices ranging from 0 to 2 LINs which are
compatible to J2602-2 and LIN 2.1
Document Number: MC33903_4_5
Rev. 9.0, 2/2012
333990033/4//5
SYSTEM BASIS CHIP
EK Suffix (Pb-free)
98ASA10556D
32-PIN SOIC
EK Suffix (Pb-free)
98ASA10506D
54-PIN SOIC
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2010 - 2012. All rights reserved.
Free Datasheet http://www.datasheet4u.com/




33904 pdf, 반도체, 판매, 대치품
SIMPLIFIED APPLICATION DIAGRAMS
VBAT
VBAT
CAN Bus
33904
D1 Q2
(5.0 V/3.3 V)
Q1*
VBAUX VCAUX VSUP1 VAUX VE VB VDD
VSUP2
SAFE
DBG
GND
VSENSE
I/O-0
RST
INT
MOSI
SCLK
MISO
CS
MUX-OUT
SPI
I/O-1
CANH
SPLIT
CANL
5V-CAN
TXD
RXD
I/O-2
I/O-3
Figure 3. 33904 Simplified Application Diagram
* = Optional
VDD
MCU
A/D
VBAT
D1
CAN Bus
33903
VSUP1 VSUP2
DBG
SAFE
GND
I/O-0
VDD
RST
INT
MOSI
SCLK
MISO
CS
SPI
CANH
SPLIT
CANL
5V-CAN
TXD
RXD
VDD
MCU
Figure 4. 33903 Simplified Application Diagram
33903/4/5
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
Free Datasheet http://www.datasheet4u.com/

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33904 전자부품, 판매, 대치품
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. MC33905 Device Variations - (All devices rated at TA = -40 TO 125 °C)
Freescale Part Number
Version VDD Output
LIN Wake-up Input / LIN Master
(1), (2)
Voltage Interface(s)
Termination
Package
VAUX VSENSE MUX
MC33905D (Dual LIN)
MCZ33905BD3EK/R2
MCZ33905CD3EK/R2
MCZ33905D5EK/R2
MCZ33905BD5EK/R2
MCZ33905CD5EK/R2
B
3.3 V
C
B 5.0 V
C
2 Wake-up + 2 LIN terms
2
or
3 Wake-up + 1 LIN terms
SOIC 54 pin
Yes
Yes
Yes
or exposed pad
4 Wake-up + no LIN terms
MC33905S (Single LIN)
MCZ33905BS3EK/R2
MCZ33905CS3EK/R2
MCZ33905S5EK/R2
MCZ33905BS5EK/R2
B
3.3 V
C
B 5.0 V
3 Wake-up + 1 LIN terms
1 or
4 Wake-up + no LIN terms
Yes Yes Yes
MCZ33905CS5EK/R2
C
Notes
1. Design changes in the “B” version resolved VSUP slow ramp up issues, enhanced device current consumption and improved oscillator
stability. “B” version has an errata linked to the SPI operation.
2. “C” versions are recommended for new designs. Design changes in the “C” version resolve the SPI deviation of all prior versions, and
does not have the RxD short to ground detection feature.
Table 2. MC33904 Device Variations - (All devices rated at TA = -40 TO 125 °C)
Freescale Part Number
Version VDD Output
LIN Wake-up Input / LIN Master
(3), (4)
Voltage Interface(s)
Termination
MC33904
Package
VAUX VSENSE MUX
MCZ33904B3EK/R2
MCZ33904C3EK/R2
MCZ33904A5EK/R2
MCZ33904B5EK/R2
B
3.3 V
C
A
B 5.0 V
0
4 Wake-up
SOIC 32 pin
exposed pad
Yes
Yes
Yes
MCZ33904C5EK/R2
C
Notes
3. Design changes in the “B” version resolved VSUP slow ramp up issues, enhanced device current consumption and improved oscillator
stability. “B” version has an errata linked to the SPI operation.
4. “C” versions are recommended for new designs. Design changes in the “C” version resolve the SPI deviation of all prior versions, and
does not have the RxD short to ground detection feature.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33903/4/5
7
Free Datasheet http://www.datasheet4u.com/

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