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PDF ADF4154 Data sheet ( Hoja de datos )
| Número de pieza | ADF4154 | |
| Descripción | Fractional-N Frequency Synthesizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
Fractional-N Frequency Synthesizer
ADF4154
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 4 GHz
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable dual-modulus prescaler 4/5, 8/9
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with the ADF4110/ADF4111/
ADF4112/ADF4113, ADF4106, ADF4153
Programmable modulus on fractional-N synthesizer
Trade-off noise vs. spurious performance
Fast-lock mode with built-in timer
Loop filter design possible with ADIsimPLL™
APPLICATIONS
Base stations for mobile radio (WiMAX, PHS, GSM, PCS, DCS,
CDMA, PMR, W-CDMA, supercell 3G)
Wireless handsets (PMR, GSM, PCS, DCS, CDMA, WCDMA)
CATV equipment
Wireless LANs
Communications test equipment
The ADF4154 is a fractional-N frequency synthesizer that
implements local oscillators in the up conversion and down
conversion sections of wireless receivers and transmitters. It
consists of a low noise digital phase frequency detector (PFD),
a precision charge pump, and a programmable reference divider.
There is a Σ-Δ based fractional interpolator to allow programmable
fractional-N division. The INT, FRAC, and MOD registers define
an overall N-divider (N = (INT + (FRAC/MOD))). In addition,
the 4-bit reference counter (R-counter) allows selectable REFIN
frequencies at the PFD input. A complete phase-locked loop (PLL)
can be implemented if the synthesizer is used with an external
loop filter and a voltage-controlled oscillator (VCO).
A key feature of the ADF4154 is the fast-lock mode with a built-
in timer. The user can program a predetermined countdown
time value so that the PLL remains in wide bandwidth mode,
instead of the user having to control this time externally.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP SDVDD
RSET
ADF4154
REFERENCE
REFIN
MUXOUT
×2
DOUBLER
HIGH Z
OUTPUT
MUX
4-BIT
R COUNTER
VDD
DGND
LOCK
DETECT
VDD
RDIV
NDIV
FAST-LOCK
SWITCH
THIRD ORDER
FRACTIONAL
INTERPOLATOR
+ PHASE
FREQUENCY
DETECTOR
–
CHARGE
PUMP
CURRENT
SETTING
RFCP3 RFCP2 RFCP1
N COUNTER
CP
RFINA
RFINB
CLOCK
DATA
LE
24-BIT
DATA
REGISTER
FRACTION MODULUS
REG
REG
INTEGER REG
AGND
DGND
Figure 1.
CPGND
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.
1 page  
ADF4154
Data Sheet
TIMING CHARACTERISTICS
AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm
referred to 50 Ω.
Table 2.
Parameter1
t1
t2
t3
t4
t5
t6
t7
Limit at TMIN to TMAX (B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE setup time
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK high duration
CLOCK low duration
CLOCK to LE setup time
LE pulse width
1 Guaranteed by design, but not production tested.
CLOCK
t4 t5
DATA
DB23 (MSB)
LE
t1
LE
t2 t3
DB22
DB2
DB1
(CONTROL BIT C2)
Figure 2. Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Rev. C | Page 4 of 24
5 Page 
ADF4154
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4154 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 (see Table 8).
Figure 18 shows the MUXOUT section in block diagram form.
The N-channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When lock has been detected, the lock detect is high with
narrow low-going pulses.
DVDD
LOGIC LOW
ANALOG LOCK DETECT
R-DIVIDER OUTPUT
N-DIVIDER OUTPUT
FAST-LOCK CONTROL
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
LOGIC HIGH
MUX
CONTROL
MUXOUT
DGND
Figure 18. MUXOUT Schematic
INPUT SHIFT REGISTERS
The ADF4154 digital section includes a 4-bit R value, a 9-bit
RF N value, a 12-bit RF FRAC value, and a 12-bit interpolator
modulus value/fast-lock timer. Data is clocked MSB first into
the 24-bit shift register on each rising edge of CLK.
Data Sheet
Data is transferred from the shift register to one of four latches
on the rising edge of LE. The destination latch is determined by
the state of the two control bits (C2 and C1) in the shift register.
These are the two LSBs, DB1 and DB0, as shown in Figure 2.
The truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed.
PROGRAM MODES
Table 5 through Table 9 show how to set up the program modes
in the ADF4154.
The ADF4154 programmable modulus is double buffered,
meaning that two events must occur before the part can use a
new modulus value. The first event is that the new modulus value
must be latched into the device by writing to the R-divider register,
and the second event is that a new write must be performed on
the N-divider register. Therefore, whenever the modulus value
is updated, the N-divider register must be written to so that the
modulus value is loaded correctly.
Table 5. C2 and C1 Truth Table
Control Bits
C2 C1 Data Latch
0 0 N-divider register
0 1 R-divider register
1 0 Control register
1 1 Noise and spur register
Rev. C | Page 10 of 24
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ADF4154.PDF ] | |
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