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부품번호 ADF4159 기능
기능 Fractional-N Frequency Synthesizer
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ADF4159 데이터시트, 핀배열, 회로
Data Sheet
Direct Modulation/Fast Waveform Generating,
13 GHz, Fractional-N Frequency Synthesizer
ADF4159
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 13 GHz
High and low speed FMCW ramp generation
25-bit fixed modulus allows subhertz frequency resolution
PFD frequencies up to 110 MHz
Normalized phase noise floor of −224 dBc/Hz
FSK and PSK functions
Sawtooth, triangular, and parabolic waveform generation
Ramp superimposed with FSK
Ramp with 2 different sweep rates
Ramp delay, frequency readback, and interrupt functions
Programmable phase control
2.7 V to 3.45 V analog power supply
1.8 V digital power supply
Programmable charge pump currents
3-wire serial interface
Digital lock detect
ESD performance: 3000 V HBM, 1000 V CDM
The ADF4159 is a 13 GHz, fractional-N frequency synthesizer
with modulation and both fast and slow waveform generation
capability. The part uses a 25-bit fixed modulus, allowing subhertz
frequency resolution.
The ADF4159 consists of a low noise digital phase frequency
detector (PFD), a precision charge pump, and a programmable
reference divider. The Σ-Δ-based fractional interpolator allows
programmable fractional-N division. The INT and FRAC registers
define an overall N divider as N = INT + (FRAC/225).
The ADF4159 can be used to implement frequency shift keying
(FSK) and phase shift keying (PSK) modulation. Frequency sweep
modes are also available to generate various waveforms in the
frequency domain, for example, sawtooth and triangular wave-
forms. The ADF4159 features cycle slip reduction circuitry, which
enables faster lock times without the need for modifications to
the loop filter.
APPLICATIONS
FMCW radars
Communications test equipment
Communications infrastructure
Control of all on-chip registers is via a simple 3-wire interface. The
ADF4159 operates with an analog power supply in the range of
2.7 V to 3.45 V and a digital power supply in the range of 1.62 V
to 1.98 V. The device can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD SDVDD
VP
RSET
ADF4159
REFIN
×2
DOUBLER
5-BIT
R COUNTER
÷2
DIVIDER
HIGH-Z
MUXOUT
OUTPUT
MUX
CE
TXDATA
DGND
SDOUT
DVDD
RDIV
NDIV
LOCK
DETECT
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
+ PHASE
FREQUENCY
DETECTOR
REFERENCE
SW2
CHARGE
PUMP
CSR
FAST LOCK
SWITCH
CP
SW1
N COUNTER
+
RFINA
RFINB
CLK
DATA
LE
32-BIT
DATA
REGISTER
FRACTION
VALUE
MODULUS
225 VALUE
INTEGER
VALUE
AGND
DGND
SDGND
Figure 1.
CPGND
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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ADF4159 pdf, 반도체, 판매, 대치품
ADF4159
Data Sheet
Parameter1
NOISE CHARACTERISTICS
Normalized Phase Noise Floor3
Integer-N Mode
Fractional-N Mode
Normalized 1/f Noise (PN1_f)4
Phase Noise Performance5
12,002 MHz Output6
Min Typ Max Unit Test Conditions/Comments
−224
−217
−120
−96
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
PLL loop BW = 1 MHz
FRAC = 0
Measured at 10 kHz offset, normalized
to 1 GHz
At VCO output
At 50 kHz offset, 100 MHz PFD frequency
1 Operating temperature: −40°C to +125°C.
2 Guaranteed by design. Sample tested to ensure compliance.
3 This specification can be used to calculate phase noise for any application. Use the formula ((Normalized Phase Noise Floor) + 10 log(fPFD) + 20 logN) to calculate
in-band phase noise performance as seen at the VCO output.
4 The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)
and at an offset frequency (f) is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
5 The phase noise is measured with the EV-ADF4159EB3Z and the Rohde & Schwarz FSUP signal source analyzer.
6 fREFIN = 100 MHz; fPFD = 100 MHz; offset frequency = 50 kHz; RFOUT = 12,002 MHz; N = 120.02; loop bandwidth = 250 kHz.
TIMING SPECIFICATIONS
AVDD = VP = 2.7 V to 3.45 V, DVDD = SDVDD = 1.8 V, AGND = DGND = SDGND = CPGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 Ω,
unless otherwise noted.
Table 2. Write Timing
Parameter
Limit at TMIN to TMAX
t1 20
t2 10
t3 10
t4 25
t5 25
t6 10
t7 20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Write Timing Diagram
CLK
t4 t5
DATA
DB31 (MSB)
LE
t1
LE
t2 t3
DB30
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
Figure 2. Write Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Rev. B | Page 4 of 36
Free Datasheet http://www.datasheet4u.com/

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ADF4159 전자부품, 판매, 대치품
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADF4159
CPGND 1
AGND 2
AGND 3
RFINB 4
RFINA 5
AVDD 6
ADF4159
TOP VIEW
(Not to Scale)
18 SDVDD
17 MUXOUT
16 LE
15 DATA
14 CLK
13 CE
NOTES
1. THE LFCSP HAS AN EXPOSED PAD
THAT MUST BE CONNECTED TO AGND.
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
CPGND
Charge Pump Ground. This pin is the ground return path for the charge pump.
2, 3
AGND
Analog Ground.
4
RFINB
Complementary Input to the RF Prescaler. Decouple this pin to the ground plane with a small bypass capacitor,
typically 100 pF.
5
RFINA
Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
6, 7, 8
AVDD
Positive Power Supply for the RF Section. Place decoupling capacitors to the ground plane as close as possible
to these pins.
9
REFIN
Reference Input. This CMOS input has a nominal threshold of DVDD/2 and an equivalent input resistance of 100 kΩ.
It can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
10
DGND
Digital Ground.
11
SDGND
Digital Σ-Δ Modulator Ground. This pin is the ground return path for the Σ-Δ modulator.
12
TXDATA
Transmit Data Pin. This pin provides the data to be transmitted in FSK or PSK mode and also controls some
ramping functionality.
13 CE
Chip Enable (1.8 V Logic). A logic low on this pin powers down the device and places the charge pump output
into three-state mode.
14 CLK Serial Clock Input. This input is used to clock in the serial data to the registers. The data is latched into the input
shift register on the CLK rising edge. This input is a high impedance CMOS input.
15
DATA
Serial Data Input. The serial data is loaded MSB first; the three LSBs are the control bits. This input is a high
impedance CMOS input.
16 LE
Load Enable Input. When LE is high, the data stored in the input shift register is loaded into one of the eight
latches; the latch is selected using the control bits. This input is a high impedance CMOS input.
17 MUXOUT Multiplexer Output. This pin allows various internal signals to be accessed externally.
18
SDVDD
Power Supply for the Digital Σ-Δ Modulator. Place decoupling capacitors to the ground plane as close as
possible to this pin.
19
DVDD
Positive Power Supply for the Digital Section. Place decoupling capacitors to the digital ground plane as close
as possible to this pin.
20, 21
SW1, SW2 Switches for Fast Lock.
22 VP
Charge Pump Power Supply. The voltage on this pin must be greater than or equal to AVDD.
23 RSET Connecting a resistor between this pin and ground sets the maximum charge pump output current. The
relationship between ICP and RSET is as follows:
ICP_MAX = 24.48/RSET
where:
ICP_MAX = 4.8 mA.
RSET = 5.1 kΩ.
24 CP
Charge Pump Output. When the charge pump is enabled, this output provides ±ICP to the external loop filter,
which, in turn, drives the external VCO.
25
EPAD
Exposed Pad. The LFCSP has an exposed pad that must be connected to AGND.
Rev. B | Page 7 of 36
Free Datasheet http://www.datasheet4u.com/

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