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PDF AD7940 Data sheet ( Hoja de datos )
| Número de pieza | AD7940 | |
| Descripción | 14-Bit ADC | |
| Fabricantes | Analog Devices | |
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FEATURES
Fast throughput rate: 100 kSPS
Specified for VDD of 2.5 V to 5.5 V
Low power
4 mW typ at 100 kSPS with 3 V supplies
17 mW typ at 100 kSPS with 5 V supplies
Wide input bandwidth:
81 dB SINAD at 10 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Standby mode: 0.5 µA max
6-Lead SOT-23 and 8-Lead MSOP packages
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Remote data acquisition systems
3 mW, 100 kSPS,
14-Bit ADC in 6-Lead SOT-23
AD7940
FUNCTIONAL BLOCK DIAGRAM
VDD
14-BIT SUCCESSIVE
VIN T/H
APPROXIMATION
ADC
AD7940
CONTROL
LOGIC
SCLK
SDATA
CS
GND
Figure 1.
Table 1. 16-Bit and 14-Bit ADC (MSOP and SOT-23)
Type
100 kSPS 250 kSPS 500 kSPS
16-Bit True Differential
AD7684 AD7687 AD7688
16-Bit Pseudo Differential AD7683 AD7685 AD7686
16-Bit Unipolar
AD7680
14-Bit True Differential
AD7944 AD7947
14-Bit Pseudo Differential
AD7942 AD7946
14-Bit Unipolar
AD7940
GENERAL DESCRIPTION
The AD79401 is a 14-bit, fast, low power, successive
approximation ADC. The part operates from a single 2.50 V to
5.5 V power supply and features throughput rates up to 100 kSPS.
The part contains a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 7 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is also initiated at this
point. There are no pipelined delays associated with the part.
The AD7940 uses advanced design techniques to achieve very
low power dissipation at fast throughput rates. The reference for
the part is taken internally from VDD, which allows the widest
dynamic input range to the ADC. Thus, the analog input range
for this part is 0 V to VDD. The conversion rate is determined by
the SCLK frequency.
This part features a standard successive approximation ADC
with accurate control of the sampling instant via a CS input and
once off conversion control.
PRODUCT HIGHLIGHTS
1. First 14-bit ADC in a SOT-23 package.
2. High throughput with low power consumption.
3. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced when a power-down mode is used while not
converting. The part also features a shutdown mode to
maximize power efficiency at lower throughput rates.
Power consumption is 0.5 µA max when in shutdown.
4. Reference derived from the power supply.
5. No pipeline delay.
1Protected by US. Patent No. 6,681,332.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/
1 page  
AD7940
TIMING SPECIFICATIONS
Sample tested at initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from
a voltage level of 1.6 V.
VDD = 2.50 V to 5.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
fSCLK1
tCONVERT
tQUIET
t1
t2
t3 2
t42
t5
t6
t7
t8 3
t4
POWER-UP
Limit at TMIN, TMAX
3V 5V
250 250
2.5 2.5
16 × tSCLK
50
16 × tSCLK
50
10
10
48
120
0.4 tSCLK
0.4 tSCLK
10
45
1
10
10
35
80
0.4 tSCLK
0.4 tSCLK
10
35
1
Unit
kHz min
MHz max
min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
µs typ
Description
Minimum quiet time required between bus relinquish and start of
next conversion
Minimum CS pulse width
CS to SCLK setup time
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to SDATA high impedance
Power up time from full power-down
1 Mark/space ratio for the SCLK input is 40/60 to 60/40.
2 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
3 t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
4 See the Power vs. Throughput Rate section.
200µA
IOL
TO OUTPUT
PIN CL
50pF
1.6V
200µA
IOH
Figure 2. Load Circuit for Digital Output Timing Specification
Rev. A | Page 5 of 20
Free Datasheet http://www.datasheet4u.com/
5 Page 
CIRCUIT INFORMATION
The AD7940 is a fast, low power, 14-bit, single-supply ADC.
The part can be operated from a 2.50 V to 5.5 V supply. When
operated at either 5 V or 3 V supply, the AD7940 is capable of
throughput rates of 100 kSPS when provided with a 2.5 MHz
clock.
The AD7940 provides the user with an on-chip track-and-hold
ADC and a serial interface housed in a tiny 6-lead SOT-23
package or in an 8-lead MSOP package, which offer the user
considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the part and also
provides the clock source for the successive approximation
ADC. The analog input range for the AD7940 is 0 V to VDD. An
external reference is not required for the ADC nor is there a
reference on-chip. The reference for the AD7940 is derived from
the power supply and thus gives the widest dynamic input range.
The AD7940 also features a power-down option to save power
between conversions. The power-down feature is implemented
across the standard serial interface as described in the Modes of
Operation section.
CONVERTER OPERATION
The AD7940 is a 14-bit, successive approximation ADC based
around a capacitive DAC. The AD7940 can convert analog
input signals in the 0 V to VDD range. Figure 11 and Figure 12
show simplified schematics of the ADC. The ADC comprises of
control logic, SAR, and a capacitive DAC. Figure 11 shows the
ADC during its acquisition phase. SW2 is closed and SW1 is in
Position A. The comparator is held in a balanced condition and
the sampling capacitor acquires the signal on the selected VIN
channel.
CAPACITIVE
DAC
A
VIN
SAMPLING
CAPACITOR
SW1
B
ACQUISITION
PHASE
SW2
VDD/2
CONTROL
LOGIC
COMPARATOR
Figure 11. ADC Acquisition Phase
When the ADC starts a conversion, SW2 will open and SW1
will move to Position B, causing the comparator to become
unbalanced (Figure 12). The control logic and the capacitive
DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into
a balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code (see the ADC Transfer Function section).
AD7940
CAPACITIVE
DAC
A
VIN
SAMPLING
CAPACITOR
SW1
B
CONVERSION
PHASE
SW2
VDD/2
CONTROL
LOGIC
COMPARATOR
Figure 12. ADC Conversion Phase
ANALOG INPUT
Figure 13 shows an equivalent circuit of the analog input
structure of the AD7940. The two diodes, D1 and D2, provide
ESD protection for the analog inputs. Care must be taken to
ensure that the analog input signal never exceeds the supply
rails by more than 300 mV. This will cause these diodes to
become forward-biased and to start conducting current into the
substrate. The maximum current these diodes can conduct
without causing irreversible damage to the part is 10 mA.
Capacitor C1 in Figure 13 is typically about 5 pF and primarily
can be attributed to pin capacitance. Resistor R1 is a lumped
component made up of the on resistance of a switch (track-and-
hold switch). This resistor is typically about 25 Ω. Capacitor C2
is the ADC sampling capacitor and has a capacitance of 25 pF
typically. For ac applications, removing high frequency
components from the analog input signal is recommended by
use of an RC low-pass filter on the relevant analog input pin. In
applications where harmonic distortion and signal-to-noise
ratio are critical, the analog input should be driven from a low
impedance source. Large source impedances will significantly
affect the ac performance of the ADC. This may necessitate the
use of an input buffer amplifier. The choice of the op amp will
be a function of the particular application. When no amplifier is
used to drive the analog input, the source impedance should be
limited to low values. The maximum source impedance will
depend on the amount of total harmonic distortion (THD) that
can be tolerated. The THD will increase as the source impedance
increases, and performance will degrade (see Figure 8).
VDD
VIN
C1
4pF
D1
C2
R1 30pF
D2
CONVERSION PHASE - SWITCH OPEN
TRACK PHASE - SWITCH CLOSED
Figure 13. Equivalent Analog Input Circuit
Rev. A | Page 11 of 20
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD7940.PDF ] | |
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