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PDF A54SX32 Data sheet ( Hoja de datos )
| Número de pieza | A54SX32 | |
| Descripción | SX Family FPGAs | |
| Fabricantes | Actel | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de A54SX32 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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SX Family FPGAs
Leading Edge Performance
• 320 MHz Internal Performance
• 3.7 ns Clock-to-Out (Pin-to-Pin)
• 0.1 ns Input Setup
• 0.25 ns Clock Skew
Specifications
• 12,000 to 48,000 System Gates
• Up to 249 User-Programmable I/O Pins
• Up to 1,080 Flip-Flops
• 0.35 µ CMOS
SX Product Profile
Device
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
Register Cells (Dedicated Flip-Flops)
Maximum User I/Os
Clocks
JTAG
PCI
Clock-to-Out
Input Setup (external)
Speed Grades
Temperature Grades
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
PBGA
FBGA
A54SX08
8,000
12,000
768
512
256
130
3
Yes
–
3.7 ns
0.8 ns
Std, –1, –2, –3
C, I, M
84
208
100
144, 176
–
144
v3.2
™
ue
Features
• 66 MHz PCI
• CPLD and FPGA Integration
• Single-Chip Solution
• 100% Resource Utilization with 100% Pin Locking
• 3.3 V and 5.0 V Operation with 5.0 V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug Capability
with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
A54SX16
16,000
24,000
1,452
924
528
175
3
Yes
–
3.9 ns
0.5 ns
Std, –1, –2, –3
C, I, M
–
208
100
176
–
–
A54SX16P
16,000
24,000
1,452
924
528
175
3
Yes
Yes
4.4 ns
0.5 ns
Std, –1, –2, –3
C, I, M
–
208
100
144, 176
–
–
A54SX32
32,000
48,000
2,880
1,800
1,080
249
3
Yes
–
4.6 ns
0.1 ns
Std, –1, –2, –3
C, I, M
–
208
–
144, 176
313, 329
–
June 2006
© 2006 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
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1 page  
SX Family FPGAs
SX Family FPGAs
General Description
The Actel SX family of FPGAs features a sea-of-modules
architecture that delivers device performance and
integration levels not currently achieved by any other
FPGA architecture. SX devices greatly simplify design
time, enable dramatic reductions in design costs and
power consumption, and further decrease time to
market for performance-intensive applications.
The Actel SX architecture features two types of logic
modules, the combinatorial cell (C-cell) and the register
cell (R-cell), each optimized for fast and efficient
mapping of synthesized logic functions. The routing and
interconnect resources are in the metal layers above the
logic modules, providing optimal use of silicon. This
enables the entire floor of the device to be spanned with
an uninterrupted grid of fine-grained, synthesis-friendly
logic modules (or “sea-of-modules”), which reduces the
distance signals have to travel between logic modules. To
minimize signal propagation delay, SX devices employ
both local and general routing resources. The high-speed
local routing resources (DirectConnect and FastConnect)
enable very fast local signal propagation that is optimal
for fast counters, state machines, and datapath logic.
The general system of segmented routing tracks allows
any logic module in the array to be connected to any
other logic or I/O module. Within this system,
propagation delay is minimized by limiting the number
of antifuse interconnect elements to five (90 percent of
connections typically use only three antifuses). The
unique local and general routing structure featured in
SX devices gives fast and predictable performance,
allows 100 percent pin-locking with full logic utilization,
enables concurrent PCB development, reduces design
time, and allows designers to achieve performance goals
with minimum effort.
Further complementing SX’s flexible routing structure is
a hardwired, constantly loaded clock network that has
been tuned to provide fast clock propagation with
minimal clock skew. Additionally, the high performance
of the internal logic has eliminated the need to embed
latches or flip-flops in the I/O cells to achieve fast clock-
to-out or fast input setup times. SX devices have easy to
use I/O cells that do not require HDL instantiation,
facilitating design reuse and reducing design and
verification time.
SX Family Architecture
The SX family architecture was designed to satisfy next-
generation performance and integration requirements
for production-volume designs in a broad range of
applications.
Programmable Interconnect Element
The SX family provides efficient use of silicon by locating
the routing interconnect resources between the Metal 2
(M2) and Metal 3 (M3) layers (Figure 1-1 on page 1-2).
This completely eliminates the channels of routing and
interconnect resources between logic modules (as
implemented on SRAM FPGAs and previous generations
of antifuse FPGAs), and enables the entire floor of the
device to be spanned with an uninterrupted grid of logic
modules.
Interconnection between these logic modules is achieved
using The Actel patented metal-to-metal programmable
antifuse interconnect elements, which are embedded
between the M2 and M3 layers. The antifuses are
normally open circuit and, when programmed, form a
permanent low-impedance connection.
The extremely small size of these interconnect elements
gives the SX family abundant routing resources and
provides excellent protection against design pirating.
Reverse engineering is virtually impossible because it is
extremely difficult to distinguish between programmed
and unprogrammed antifuses, and there is no
configuration bitstream to intercept.
Additionally, the interconnect elements (i.e., the
antifuses and metal tracks) have lower capacitance and
lower resistance than any other device of similar
capacity, leading to the fastest signal propagation in the
industry.
Logic Module Design
The SX family architecture is described as a “sea-of-
modules” architecture because the entire floor of the
device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. The Actel SX family provides two types of logic
modules, the register cell (R-cell) and the combinatorial
cell (C-cell).
v3.2
1-1
Free Datasheet http://www.datasheet4u.com/
5 Page 
SX Family FPGAs
16 Channels
Serial Connection
Silicon
Explorer II
TDI
TCK
TMS
TDO
SX FPGA
Figure 1-8 • Probe Setup
PRA
PRB
Programming
Device programming is supported through Silicon
Sculptor series of programmers. In particular, Silicon
Sculptor II are compact, robust, single-site and multi-site
device programmer for the PC.
With standalone software, Silicon Sculptor II allows
concurrent programming of multiple units from the
same PC, ensuring the fastest programming times
possible. Each fuse is subsequently verified by Silicon
Sculptor II to insure correct programming. In addition,
integrity tests ensure that no extra fuses are
programmed. Silicon Sculptor II also provides extensive
hardware self-testing capability.
The procedure for programming an SX device using
Silicon Sculptor II are as follows:
1. Load the .AFM file
2. Select the device to be programmed
3. Begin programming
When the design is ready to go to production, Actel
offers device volume-programming services either
through distribution partners or via in-house
programming from the factory.
For more details on programming SX devices, refer to the
Programming Antifuse Devices application note and the
Silicon Sculptor II User's Guide.
3.3 V / 5 V Operating Conditions
Table 1-3 • Absolute Maximum Ratings1
Symbol
Parameter
Limits
Units
VCCR2
VCCA2
VCCI2
VCCI2
DC Supply Voltage3
DC Supply Voltage
DC Supply Voltage (A54SX08, A54SX16, A54SX32)
DC Supply Voltage (A54SX16P)
–0.3 to + 6.0
–0.3 to + 4.0
–0.3 to + 4.0
–0.3 to + 6.0
V
V
V
V
VI Input Voltage
–0.5 to + 5.5
V
VO Output Voltage
IIO I/O Source Sink Current3
–0.5 to + 3.6
–30 to + 5.0
V
mA
TSTG Storage Temperature
–65 to +150
°C
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the
Recommended Operating Conditions.
2. VCCR in the A54SX16P must be greater than or equal to VCCI during power-up and power-down sequences and during normal
operation.
3. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC +
0.5 V or less than GND – 0.5 V, the internal protection diodes will forward-bias and can draw excessive current.
v3.2
1-7
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