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HIP6020CB 데이터시트 PDF




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부품번호 HIP6020CB 기능
기능 Advanced Dual PWM and Dual Linear Power Controller
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HIP6020CB 데이터시트, 핀배열, 회로
Data Sheet
HIP6020
February 1999
File Number 4683
Advanced Dual PWM and Dual Linear
Power Controller
The HIP6020 provides the power control and protection for
four output voltages in high-performance, graphics intensive
microprocessor and computer applications. The IC
integrates two PWM controllers and two linear controllers, as
well as the monitoring and protection functions into a 28-pin
SOIC package. One PWM controller regulates the
microprocessor core voltage with a synchronous-rectified
buck converter. The second PWM controller supplies the
computer system’s AGP 1.5V or 3.3V bus power with a
standard buck converter. The linear controllers regulate
power for the 1.5V GTL bus and the 1.8V power for the
North/South Bridge core voltage and/or cache memory
circuits.
The HIP6020 includes an Intel-compatible, TTL 5-input
digital-to-analog converter (DAC) that adjusts the core PWM
output voltage from 1.3VDC to 2.05VDC in 0.05V steps and
from 2.1VDC to 3.5VDC in 0.1V increments. The precision
reference and voltage-mode control provide ±1% static
regulation. The second PWM controller’s output is user-
selectable, through a TTL-compatible signal applied at the
SELECT pin, for levels of 1.5V or 3.3V with ±3% accuracy.
The linear regulators use external N-Channel MOSFETs or
bipolar NPN pass transistors to provide fixed output voltages
of 1.5V ±3% (VOUT3) and 1.8V ±3% (VOUT4).
The HIP6020 monitors all the output voltages. A single
Power Good signal is issued when the core is within ±10% of
the DAC setting and all other outputs are above their under-
voltage levels. Additional built-in over-voltage protection for
the core output uses the lower MOSFET to prevent output
voltages above 115% of the DAC setting. The PWM
controllers’ over-current function monitors the output current
by using the voltage drop across the upper MOSFET’s
rDS(ON), eliminating the need for a current sensing resistor.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HIP6020CB
0 to 70 28 Ld SOIC
HIP6020EVAL1 Evaluation Board
PKG.
NO.
M28.3
Features
• Provides 4 Regulated Voltages
- Microprocessor Core, AGP Bus, North/South Bridge
and/or Cache Memory, and GTL Bus Power
• Drives N-Channel MOSFETs
• Linear Regulator Drives Compatible with both MOSFET
and Bipolar Series Pass Transistors
• Simple Single-Loop Control Designs
- Voltage-Mode PWM Control
• Fast PWM Converter Transient Response
- High-Bandwidth Error Amplifiers
- Full 0% to 100% Duty Ratios
• Excellent Output Voltage Regulation
- Core PWM Output: ±1% Over Temperature
- AGP Bus PWM Output: ±3% Over Temperature
- Other Outputs: ±3% Over Temperature
• TTL-Compatible 5 Bit DAC Microprocessor Core Output
Voltage Selection
- Wide Range . . . . . . . . . . . . . . . . . . . 1.3VDC to 3.5VDC
• Power-Good Output Voltage Monitor
• Over-Voltage and Over-Current Fault Monitors
- Switching Regulators Do Not Require Extra Current
Sensing Elements, Use MOSFET’s rDS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Free-Running Oscillator; Programmable From
50kHz to Over 1MHz
- Small External Component Count
Applications
Motherboard Power Regulation for Computers
Pinout
HIP6020 (SOIC)
TOP VIEW
UGATE2 1
PHASE2 2
VID4 3
VID3 4
VID2 5
VID1 6
VID0 7
PGOOD 8
OCSET2 9
VSEN2 10
SELECT 11
SS 12
FAULT/RT 13
VSEN4 14
28 VCC
27 UGATE1
26 PHASE1
25 LGATE1
24 PGND
23 OCSET1
22 VSEN1
21 FB1
20 COMP1
19 VSEN3
18 DRIVE3
17 GND
16 VAUX
15 DRIVE4
2-281
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999




HIP6020CB pdf, 반도체, 판매, 대치품
HIP6020
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V
PGOOD, RT/FAULT, DRIVE, PHASE, and
GATE Voltage . . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V
Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . GND -0.3V to 7V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 125oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX
VCC SUPPLY CURRENT
Nominal Supply Current
ICC UGATE1, LGATE1, UGATE2, DRIVE3, and
DRIVE4 Open
-9-
POWER-ON RESET
Rising VCC Threshold
Falling VCC Threshold
Rising VAUX Threshold
VAUX Threshold Hysteresis
Rising VOCSET1 Threshold
OSCILLATOR
VOCSET = 4.5V
VOCSET = 4.5V
VOCSET = 4.5V
VOCSET = 4.5V
- - 10.4
8.2 -
-
- 2.5 -
- 0.5 -
- 1.26 -
Free Running Frequency
Total Variation
FOSC
RT = OPEN
6k< RT to GND < 200k
185 200 215
-15 - +15
Ramp Amplitude
VOSC RT = Open
DAC AND STANDARD BUCK REGULATOR REFERENCE
- 1.9 -
DAC(VID0-VID4) Input Low Voltage
- - 0.8
DAC(VID0-VID4) Input High Voltage
2.0 -
DACOUT Voltage Accuracy
-1.0 - +1.0
PWM2 Reference Voltage
SELECT < 0.8V
- 1.5 -
PWM2 Reference Voltage
SELECT > 2.0V
- 3.3 -
PWM2 Reference Voltage Tolerance
-3-
1.5V AND 1.8V LINEAR REGULATORS (VOUT3 AND VOUT4)
Regulation
-3-
VSEN3 Regulation Voltage
VSEN4 Regulation Voltage
VSEN3,4 Under-Voltage Level
VSEN3,4 Under-Voltage Hysteresis
VREG3
VREG4
VSEN3UV
VSEN3 Rising
VSEN3 Falling
- 1.5 -
- 1.8 -
- 75 -
-7-
Output Drive Current
VAUX-VDRIVE > 0.6V
SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER
20 40
-
DC Gain
- 88 -
Gain-Bandwidth Product
GBWP
- 15 -
Slew Rate
SR COMP1 = 10pF
-6-
UNITS
mA
V
V
V
V
V
kHz
%
VP-P
V
V
%
V
V
%
%
V
V
%
%
mA
dB
MHz
V/µs
2-284

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HIP6020CB 전자부품, 판매, 대치품
HIP6020
two linear controllers. The first PWM controller (PWM1) is
designed to regulate the microprocessor core voltage (VOUT1).
PWM1 controller drives 2 MOSFETs (Q1 and Q2) in a
synchronous-rectified buck converter and regulates the core
voltage to a level programmed by the 5-bit digital-to-analog
converter (DAC). The second PWM controller (PWM2) is
designed to regulate the advanced graphics port (AGP) bus
voltage (VOUT2). PWM2 controller drives a MOSFET (Q3) in a
standard buck converter and regulates the output voltage to a
digitally-programmable level of 1.5V or 3.3V. Selection of either
output voltage is achieved by applying the proper logic level at
the SELECT pin. The two linear controllers supply the 1.5V
GTL bus power (VOUT3) and the 1.8V memory power (VOUT4).
Initialization
The HIP6020 automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input supply voltages. The POR monitors the
bias voltage (+12VIN) at the VCC pin, the 5V input voltage
(+5VIN) on the OCSET1 pin, and the 3.3V input voltage
(+3.3VIN) at the VAUX pin. The normal level on OCSET1 is
equal to +5VIN less a fixed voltage drop (see over-current
protection). The POR function initiates soft-start operation
after all supply voltages exceed their POR thresholds.
Soft-Start
The POR function initiates the soft-start sequence. Initially, the
voltage on the SS pin rapidly increases to approximately 1V
(this minimizes the soft-start interval). Then an internal 28µA
current source charges an external capacitor (CSS) on the SS
pin to 4.5V. The PWM error amplifiers reference inputs
(+ terminal) and outputs (COMP1 pin) are clamped to a level
proportional to the SS pin voltage. As the SS pin voltage slews
from 1V to 4V, the output clamp allows generation of PHASE
pulses of increasing width that charge the output capacitor(s).
After the output voltage increases to approximately 70% of the
set value, the reference input clamp slows the output voltage
rate-of-rise and provides a smooth transition to the final set
voltage. Additionally both linear regulators’ reference inputs are
clamped to a voltage proportional to the SS pin voltage. This
method provides a rapid and controlled output voltage rise.
Figure 6 shows the soft-start sequence for the typical
application. At T0 the SS voltage rapidly increases to
approximately 1V. At T1, the SS pin and error amplifier
output voltage reach the valley of the oscillator’s triangle
wave. The oscillator’s triangular wave form is compared to
the clamped error amplifier output voltage. As the SS pin
voltage increases, the pulse-width on the PHASE pin
increases. The interval of increasing pulse-width continues
until each PWM output reaches sufficient voltage to transfer
control to the error amplifier input reference clamp. If we
consider the 3.3V output (VOUT2) in Figure 6, this time
occurs at T2. During the interval between T2 and T3, the
error amplifier reference ramps to the final value and the
converter regulates the output a voltage proportional to the
SS pin voltage. At T3 the input clamp voltage exceeds the
reference voltage and the output voltage is in regulation.
PGOOD
0V
SOFT-START
(1V/DIV)
0V
OUTPUT
VOLTAGES
(0.5V/DIV)
VOUT2 ( = 3.3V)
VOUT1 (DAC = 2.5V)
VOUT4 ( = 1.8V)
VOUT3 ( = 1.5V)
0V
T0 T1
T2
TIME
T3
FIGURE 3. SOFT-START INTERVAL
T4
The remaining outputs are also programmed to follow the SS
pin voltage. The PGOOD signal toggles ‘high’ when all output
voltage levels have exceeded their under-voltage levels. See
the Soft-Start Interval section under Applications Guidelines
for a procedure to determine the soft-start interval.
Fault Protection
All four outputs are monitored and protected against extreme
overload. A sustained overload on any output or an over-
voltage on VOUT1 output (VSEN1) disables all outputs and
drives the FAULT/RT pin to VCC.
LUV
OC1
OC2
0.15V +
-
SS +
4V -
OV
OVER-
CURRENT
LATCH
SQ
INHIBIT
R
COUNTER
R
FAULT VCC
LATCH
UP S Q
POR
R FAULT
FIGURE 4. FAULT LOGIC - SIMPLIFIED SCHEMATIC
2-287

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부품번호상세설명 및 기능제조사
HIP6020CB

Advanced Dual PWM and Dual Linear Power Controller

Intersil Corporation
Intersil Corporation

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