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PDF HIP6021A Data sheet ( Hoja de datos )
| Número de pieza | HIP6021A | |
| Descripción | Advanced PWM and Triple Linear Power Controller | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
HIP6021A
November 1999
File Number 4793
Advanced PWM and Triple Linear Power
Controller
The HIP6021A provides the power control and protection for
four output voltages in high-performance, graphics intensive
microprocessor and computer applications. The IC
integrates a voltage-mode PWM controller and three linear
controllers, as well as the monitoring and protection
functions into a 28 lead SOIC package.
The synchronous-rectified buck converter includes an Intel-
compatible, TTL 5-input digital-to-analog converter (DAC)
that adjusts the core PWM output voltage from 1.3VDC to
2.05VDC in 0.05V steps and from 2.1VDC to 3.5VDC in 0.1V
increments. The precision reference and voltage-mode
control provide ±1% static regulation. A TTL-compatible
signal applied to the SELECT pin dictates which method of
control is used for the AGP bus power: a low state results in
linear control of the AGP bus to 1.5V, while a high state
transitions the output through a linearly controlled softstart to
3.3V, followed by full enhancement of the external MOSFET
to pass the input voltage. The other two linear regulators
provide fixed output voltages of 1.5V GTL bus power and
1.8V power for the North/South Bridge core and/or cache
memory. These levels are user-adjustable by means of an
external resistor divider and pulling the FIX pin low. All linear
controllers can employ either N-Channel MOSFETs or
bipolar NPNs for the pass transistor.
The HIP6021A monitors all the output voltages. A single
Power Good signal is issued when the core is within ±10% of
the DAC setting and all other outputs are above their under-
voltage levels. Additional built-in over-voltage protection for
the core output uses the lower MOSFET to prevent output
voltages above 115% of the DAC setting. The PWM
controller’s over-current function monitors the output current
by using the voltage drop across the upper MOSFET’s
rDS(ON).
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HIP6021ACB
0 to 70 28 Ld SOIC
HIP6021EVAL1 Evaluation Board
PKG.
NO.
M28.3
Features
• Provides 4 Regulated Voltages
- Microprocessor Core, AGP Bus, Memory, and GTL Bus
Power
• Drives N-Channel MOSFETs
• Linear Regulator Drives Compatible with both MOSFET
and Bipolar Series Pass Transistors
• Fixed or Externally Resistor-Adjustable Linear Outputs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast PWM Converter Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
• Excellent Output Voltage Regulation
- Core PWM Output: ±1% Over Temperature
- Other Outputs: ±3% Over Temperature
• TTL-Compatible 5-Bit DAC Core Output Voltage Selection
- Shutdown Feature Removed When All Inputs High
- Wide Range 1.3VDC to 3.5VDC
• Power-Good Output Voltage Monitor
• Over-Voltage and Over-Current Fault Monitors
- Switching Regulator Does Not Require Extra Current
Sensing Element, Uses Upper MOSFET’s rDS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Free-Running Oscillator; Programmable From
50kHz to Over 1MHz
- Small External Component Count
Applications
• Motherboard Power Regulation for Computers
Pinout
HIP6021A (SOIC)
TOP VIEW
DRIVE2 1
FIX 2
VID4 3
VID3 4
VID2 5
VID1 6
VID0 7
PGOOD 8
SD 9
VSEN2 10
SELECT 11
SS 12
FAULT/RT 13
VSEN4 14
28 VCC
27 UGATE
26 PHASE
25 LGATE
24 PGND
23 OCSET
22 VSEN1
21 FB
20 COMP
19 VSEN3
18 DRIVE3
17 GND
16 VAUX
15 DRIVE4
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
HIP6021A
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER
DC Gain
- 88 -
dB
Gain-Bandwidth Product
GBWP
- 15 -
MHz
Slew Rate
SR COMP = 10pF
- 6 - V/µs
PWM CONTROLLER GATE DRIVER
UGATE Source
UGATE Sink
LGATE Source
LGATE Sink
PROTECTION
IUGATE
RUGATE
ILGATE
RLGATE
VCC = 12V, VUGATE = 6V
VGATE-PHASE = 1V
VCC = 12V, VLGATE = 1V
VLGATE = 1V
-1-
- 1.7 3.5
-1-
- 1.4 3.0
A
Ω
A
Ω
VSEN1 Over-Voltage (VSEN1/DACOUT)
VSEN1 Rising
- 115 120
%
FAULT Sourcing Current
OCSET1 Current Source
Soft-Start Current
POWER GOOD
IOVP
IOCSET
ISS
VFAULT/RT = 2.0V
VOCSET = 4.5VDC
- 8.5 -
170 200 230
- 28 -
mA
µA
µA
VSEN1 Upper Threshold
(VSEN1/DACOUT)
VSEN1 Rising
108 - 110
%
VSEN1 Under-Voltage
(VSEN1/DACOUT)
VSEN1 Rising
92 - 94
%
VSEN1 Hysteresis (VSEN1/DACOUT)
Upper/Lower Threshold
-2-
%
PGOOD Voltage Low
VPGOOD IPGOOD = -4mA
- - 0.8 V
Typical Performance Curve
1000
100
RT PULLUP
TO +12V
10
RT PULLDOWN TO VSS
10 100
SWITCHING FREQUENCY (kHz)
FIGURE 1. RT RESISTANCE vs FREQUENCY
1000
5
5 Page 
HIP6021A
Shutdown
The HIP6021A features a dedicated shutdown pin (SD). A
TTL-compatible, logic high signal applied to this pin shuts
down (disables) all four outputs and discharges the soft-start
capacitor. Following a shutdown, a logic low signal
re-enables the outputs through initiation of a new soft-start
cycle. Left open this pin will asses a logic low state, due to its
internal pull-down resistor, thus enabling normal operation of
all outputs.
The PWM output does not switch until the soft-start voltage
(VSS) exceeds the oscillator’s valley voltage. The references
on each linear’s error amplifier are clamped to the soft-start
voltage. Holding the SS pin low (with an open drain or
collector signal) turns off all four regulators.
The ‘11111’ VID code also shuts down the IC.
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device over-voltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turn-
off transition of the upper PWM MOSFET. Prior to turn-off,
the upper MOSFET was carrying the full load current.
During the turn-off, current stops flowing in the upper
MOSFET and is picked up by the lower MOSFET or
Schottky diode. Any inductance in the switched current
path generates a large voltage spike during the switching
interval. Careful component selection, tight layout of the
critical components, and short, wide circuit traces minimize
the magnitude of voltage spikes. See Application Note
AN9836 for evaluation board drawings of the component
placement and the printed circuit board layout of a typical
application.
There are two sets of critical components in a DC-DC
converter using a HIP6021A controller. The switching power
components are the most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.
The power components and the controller IC should be
placed first. Locate the input capacitors, especially the high-
frequency ceramic decoupling capacitors, close to the power
switches. Locate the output inductor and output capacitors
between the MOSFETs and the load. Locate the PWM
controller close to the MOSFETs.
The critical small signal components include the bypass
capacitor for VCC and the soft-start capacitor, CSS. Locate
these components close to their connecting pins on the
control IC. Minimize any leakage current paths from SS
node, since the internal current source is only 28µA.
A multi-layer printed circuit board is recommended.
Figure 7 shows the connections of the critical components
in the converter. Note that the capacitors CIN and COUT
each represent numerous physical capacitors. Dedicate
one solid layer for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break
this plane into smaller islands of common voltage levels.
The power plane should support the input power and
output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the PHASE nodes, but do not
unnecessarily oversize these particular islands. Since the
PHASE nodes are subjected to very high dV/dt voltages,
the stray capacitor formed between these islands and the
surrounding circuitry will tend to couple switching noise.
Use the remaining printed circuit layers for small signal
wiring. The wiring traces from the control IC to the
MOSFET gate and source should be sized to carry 2A
peak currents.
PWM Controller Feedback Compensation
The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration
for a PWM voltage-mode controller. Apply the methods and
considerations only to the PWM controller.
Figure 8 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The
reference voltage level is the DAC output voltage (DACOUT).
The error amplifier (Error Amp) output (VE/A) is compared
with the oscillator (OSC) triangular wave to provide a pulse-
width modulated (PWM) wave with an amplitude of VIN at
the PHASE node. The PWM wave is smoothed by the output
filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
Gain, given by VIN/VOSC, and shaped by the output filter,
with a double pole break frequency at FLC and a zero
at FESR.
Modulator Break Frequency Equations
FLC=
-------------------1--------------------
2π × LO × CO
FESR= 2----π-----×-----E----S--1---R------×----C-----O---
The compensation network consists of the error amplifier
(internal to the HIP6021A) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with high 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet HIP6021A.PDF ] | |
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