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부품번호 HIP6500BCB 기능
기능 Multiple Linear Power Controller with ACPI Control Interface
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HIP6500BCB 데이터시트, 핀배열, 회로
TM
Data Sheet
HIP6500B
May 2000
File Number 4870
Multiple Linear Power Controller with
ACPI Control Interface
The HIP6500B complements either an HIP6020 or an HIP6021
in ACPI-compliant designs for microprocessor and computer
applications. The IC integrates two linear controllers and two
regulators, switching, monitoring and control functions into a
20-pin SOIC package. One linear controller generates the
3.3VDUAL voltage plane from the ATX supply’s 5VSB output,
powering the PCI slots through an external pass transistor
during sleep states (S3, S4/S5). A second transistor is used to
switch in the ATX 3.3V output for operation during S0 and
S1/S2 (active) operating states. The second linear controller
supplies the computer system’s 2.5V/3.3V memory power
through an external pass transistor in active states. During S3
state, an integrated pass transistor supplies the 2.5V/3.3V
sleep power. A third controller powers up the 5VDUAL plane by
switching in the ATX 5V output in active states, and the ATX
5VSB in sleep states. The two internal regulators consist of a
low current 3.3V sleep output and a dedicated, noise-free 2.5V
clock chip supply. The HIP6500B’s operating mode (active
outputs or sleep outputs) is selectable through two digital
control pins, S3 and S5. Further control of the logic governing
activation of different power states is offered through two
configuration pins, EN3VDL and EN5VDL. In active state, the
3.3VDUAL linear regulator uses an external N-Channel pass
MOSFET to connect the output directly to the 3.3V input
supplied by an ATX (or equivalent) power supply, for minimal
losses. In sleep state, power delivery on the 3.3VDUAL output is
transferred to an NPN transistor, also external to the controller.
Active state power delivery for the 2.5/3.3VMEM output is
performed through an external NPN transistor, or an NMOS
switch for the 3.3V setting. In sleep state, conduction on this
output is transferred to an internal pass transistor. The 5VDUAL
output is powered through two external MOS transistors. In
sleep states, a PMOS (or PNP) transistor conducts the current
from the ATX 5VSB output; while in active state, current flow is
transferred to an NMOS transistor connected to the ATX 5V
output. Similar to the 3.3VDUAL output, the operation of the
5VDUAL output is dictated not only by the status of the S3 and
S5 pins, but that of the EN5VDL pin as well. The 3.3VSB
internal regulator is active for as long as the ATX 5VSB voltage
is applied to the chip, and derives its output current from the
5VSB pin. The 2.5VCLK output is only active during S0 and S1,
and uses the 3V3 pin as input source for its internal pass
element.
Ordering Information
PART NUMBER
HIP6500BCB
HIP6500BEVAL1
TEMP.
RANGE (oC)
PACKAGE
0 to 70 20 Ld SOIC
Evaluation Board
PKG.
NO.
M20.3
Features
• Provides 5 ACPI-Controlled Voltages
- 5V Active/Sleep (5VDUAL)
- 3.3V Active/Sleep (3.3VDUAL)
- 2.5V/3.3V Active/Sleep (2.5/3.3VMEM)
- 3.3V Always Present (3.3VSB)
- 2.5V Clock (Active Only) (2.5VCLK)
• Excellent Output Voltage Regulation
- 3.3VDUAL Output: ±2% Over Temperature; Sleep State
Only
- 2.5V/3.3VMEM Output: ±2% Over Temperature; Both
Operational States (3.3V setting in sleep only)
- 2.5VCLK and 3.3VSB Output: ±2% Over Temperature
• Small Size
- Very Low External Component Count
• Selectable Memory Output Voltage Via FAULT/MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
Applications
Motherboard Power Regulation for ACPI-Compliant
Computers
Pinout
HIP6500B
(SOIC)
TOP VIEW
VSEN2 1
5VSB 2
3V3SB 3
3V3DLSB 4
3V3DL 5
VCLK 6
3V3 7
EN5VDL 8
S3 9
S5 10
20 EN3VDL
19 DRV2
18 5V
17 12V
16 SS
15 5VDL
14 5VDLSB
13 DLA
12 FAULT/MSEL
11 GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000




HIP6500BCB pdf, 반도체, 판매, 대치품
HIP6500B
Absolute Maximum Ratings
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
DLA, DRV2. . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V12V +0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 5VSB + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3
Recommended Operating Conditions
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ± 5%
Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V
Digital Inputs, VSX, VEN5VDL,
Ambient Temperature Range .
VEN3VDL
........
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 0 to +5.5V
0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 125oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX
VCC SUPPLY CURRENT
Nominal Supply Current
I5VSB
Shutdown Supply Current
I5VSB(OFF) VSS = 0.8V
POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS
- 30 -
- 14 -
Rising 5VSB POR Threshold
- - 4.5
5VSB POR Hysteresis
- 1.0 -
Rising 12V Threshold
- - 10.8
12V Hysteresis
- 1.0 -
Rising 3V3 and 5V Thresholds
- 90 -
3V3 and 5V Hysteresis
-5-
Soft-Start Current
Shutdown Voltage Threshold
3.3VSB LINEAR REGULATOR (VOUT1)
Regulation
ISS
VSD
- 10 -
- - 0.8
- - 2.0
3V3SB Nominal Voltage Level
3V3SB Undervoltage Rising Threshold
V3V3SB
- 3.3 -
- 2.739 -
3V3SB Undervoltage Hysteresis
- 99 -
3V3SB Output Current
2.5/3.3VMEM LINEAR REGULATOR (VOUT2)
Regulation (Note 2)
I3V3SB
5VSB = 5V
250 300
-
- - 2.0
VSEN2 Nominal Voltage Level
VSEN2 Nominal Voltage Level
VSEN2 Undervoltage Rising Threshold
VVSEN2
VVSEN2
RSEL = 1k
RSEL = 10k
- 2.5 -
- 3.3 -
- 83 -
VSEN2 Undervoltage Hysteresis (Note 3)
-3-
VSEN2 Output Current
IVSEN2
5VSB = 5V
250 300
-
UNITS
mA
mA
V
V
V
V
%
%
µA
V
%
V
V
mV
mA
%
V
V
%
%
mA
4

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HIP6500BCB 전자부품, 판매, 대치품
HIP6500B
3V3SB (Pin 3)
This pin is the output of the internal 3.3VSB regulator
(VOUT1). This internal regulator operates continuously for as
long as the 5VSB bias voltage is applied to the HIP6500B.
This pin is monitored for under-voltage events.
VCLK (Pin 6)
This pin is the output of the internal 2.5V clock chip regulator
(VOUT4). This internal regulator operates only in active
states (S0, S1) and is shut off during any sleep state,
regardless of the configuration of the chip. This pin is
monitored for under-voltage events.
Description
Operation
The HIP6500B controls 5 output voltages (Refer to Figures
1, 2, and 3). It is designed for microprocessor computer
applications with 3.3V, 5V, 5VSB, and 12V bias input from an
ATX power supply. The IC is composed of two linear
controllers supplying the PCI slots’ 3.3VAUX power (VOUT3)
and the 2.5V RDRAM or 3.3V SDRAM memory power
(VOUT2), two linear regulators providing an always-present
3.3VSB (VOUT1), and a dedicated 2.5V clock chip supply
(VOUT4), a dual switch controller supplying the 5VDUAL
voltage (VOUT5), as well as all the control and monitoring
functions necessary for complete ACPI implementation.
Initialization
The HIP6500B automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5VSB input supply voltage, initiating 3.3VSB
soft-start operation after exceeding POR threshold. At 3ms
(typically) after 3.3VSB finishes its ramp-up, the ENxVDL
status and the memory voltage (VMEM) setting are latched in
and the chip proceeds to ramp up the remainder of the
voltages, as required.
Operational Truth Tables
The EN3VDL and EN5VDL pins offer a choice of 4
configurations in terms of the overall system architecture
and supported features. Tables 1-3 describe the truth
combinations pertaining to each of the three outputs.
TABLE 1. 3.3VDUAL OUTPUT (VOUT3) TRUTH TABLE
EN3VDL
0
S5 S3 3V3DL
COMMENTS
1 1 3.3V S0, S1 States (Active)
0 1 0 3.3V S3
0 0 1 Note Maintains Previous State
0 0 0 3.3V S4/S5
1 1 1 3.3V S0, S1 States (Active)
1 1 0 3.3V S3
1 0 1 Note Maintains Previous State
1
00
0V S4/S5
NOTE: Combination Not Allowed.
As seen in Table 1, EN3VDL simply controls whether the
3.3VDUAL plane remains powered up during S4/S5 sleep
state.
TABLE 2. 5VDUAL OUTPUT (VOUT5) TRUTH TABLE
EN5VDL
0
S5 S3
11
5VDL
5V
COMMENTS
S0, S1 States (Active)
0
10
0V S3
0 0 1 Note Maintains Previous State
0
00
0V S4/S5
1
11
5V S0, S1 States (Active)
1
10
5V S3
1 0 1 Note Maintains Previous State
1
00
5V S4/S5
NOTE: Combination Not Allowed.
Very similarly, Table 2 details the fact that EN5VDL status
controls whether the 5VDUAL plane supports the S3-S5
sleep states.
TABLE 3. 2.5/3.3VMEM OUTPUT (VOUT2) TRUTH TABLE
RSEL S5 S3 2.5/3.3VMEM
COMMENTS
1k1 1
2.5V
S0, S1 States (Active)
1k1 0
2.5V
S3
1k0 1
Note
Maintains Previous State
1k0 0
0V S5
10k1
1
3.3V
S0, S1 States (Active)
10k1
0
3.3V
S3
10k0
1
Note
Maintains Previous State
10k0
0
0V S5
NOTE: Combination Not Allowed.
As seen in Table 3, 2.5/3.3VMEM output is maintained in S3
(suspend to RAM) sleep state only. The dual-voltage support
accommodates both SDRAM as well as RDRAM type
memories.
Not shown in any of the tables are the 3.3VSB and the
2.5VCLK outputs. The 3.3VSB output powers up as soon as
the 5VSB ATX output is available. The 2.5VCLK output
operation is restricted by the chip’s POR and is only
available in active state (S0, S1). For additional information,
see the soft-start sequence diagrams.
Additionally, the internal circuitry does not allow the
transition from an S3 (suspend to RAM) state to an S4/S5
(suspend to disk/soft off) state or vice versa. The only ‘legal’
transitions are from an active state (S0, S1) to a sleep state
(S3, S5) and vice versa.
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부품번호상세설명 및 기능제조사
HIP6500BCB

Multiple Linear Power Controller with ACPI Control Interface

Intersil Corporation
Intersil Corporation

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