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부품번호 HIP6502CB 기능
기능 Multiple Linear Power Controller with ACPI Control Interface
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HIP6502CB 데이터시트, 핀배열, 회로
Data Sheet
HIP6502
December 1999 File Number 4775.1
Multiple Linear Power Controller with
ACPI Control Interface
The HIP6502 complements either an HIP6020 or an
HIP6021 in ACPI-compliant designs for microprocessor and
computer applications. The IC integrates four linear
controllers/regulators, switching, monitoring and control
functions into a 20-pin SOIC package. One linear controller
generates the 3.3VDUAL/3.3VSB voltage plane from the ATX
supply’s 5VSB output, powering the south bridge and the
PCI slots through an external pass transistor during sleep
states (S3, S4/S5). A second transistor is used to switch in
the ATX 3.3V output for operation during S0 and S1/S2
(active) operating states. Two linear controllers/regulators
supply a choice of either or both of the computer system’s
2.5V or 3.3V memory power through external pass
transistors in active states. During sleep states, integrated
pass transistors supply the sleep power. Another controller
powers up the 5VDUAL plane by switching in the ATX 5V
output in active states, and the ATX 5VSB in sleep states.
One internal regulator outputs a dedicated, noise-free 2.5V
clock chip supply. The HIP6502’s operating mode (active
outputs or sleep outputs) is selectable through two digital
control pins, S3 and S5. Enabling sleep state support on the
5VDUAL output is offered through the EN5VDL pin. In active
state, the 3.3VDUAL and 3.3VMEM linear regulators use
external N-channel pass MOSFETs to connect the outputs
directly to the 3.3V input supplied by an ATX (or equivalent)
power supply, for minimal losses. In sleep state, power
delivery on both outputs is transferred to NPN transistors -
external to the controller on the 3.3VDUAL, internal on the
3.3VMEM. Active state regulation on the 2.5VMEM output is
performed through an external NPN transistor. In sleep
state, conduction on this output is transferred to an internal
pass transistor. The 5VDUAL output is powered through two
external MOS transistors. In sleep states, a PMOS (or PNP)
transistor conducts the current from the ATX 5VSB output;
while in active state, current flow is transferred to an NMOS
transistor connected to the ATX 5V output. The operation of
the 5VDUAL output is dictated not only by the status of the
S3 and S5 pins, but that of the EN5VDL pin as well. The
3.3VDUAL/3.3VSB output is active for as long as the ATX
5VSB voltage is applied to the chip. The 2.5VCLK output is
only active during S0 and S1/S2, and uses the 3V3 pin as
input source for its internal pass element.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HIP6502CB
0 to 70 20 Ld SOIC
HIP6502EVAL1 Evaluation Board
PKG.
NO.
M20.3
Features
• Provides 5 ACPI-Controlled Voltages
- 5VDUAL USB/Keyboard/Mouse (Active/Sleep)
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN (Active/Sleep)
- 2.5VMEM RDRAM (Active/Sleep)
- 3.3VMEM SDRAM (Active/Sleep)
- 2.5VCLK Clock/Processor Terminations (Active Only)
• Excellent Output Voltage Regulation
- 3.3VDUAL/3.3VSB Output: ±2.0% Over Temperature;
Sleep State Only
- 2.5VMEM and 3.3VMEM Output: ±2.0% Over
Temperature; Both Operational States (3.3VMEM in
sleep only)
- 2.5VCLK Output: ±2.0% Over Temperature
• Small Size
- Very Low External Component Count
• Dual Memory Voltage Support Via MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
- Both 2.5V and 3.3V for Flexible Systems
• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
Applications
Motherboard Power Regulation for ACPI-Compliant
Computers
Pinout
HIP6502
(SOIC)
TOP VIEW
VSEN2 1
5VSB 2
VSEN1 3
3V3DLSB 4
3V3DL 5
VCLK 6
3V3 7
EN5VDL 8
S3 9
S5 10
20 MSEL
19 DRV2
18 5V
17 12V
16 SS
15 5VDL
14 5VDLSB
13 DLA
12 FAULT
11 GND
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999




HIP6502CB pdf, 반도체, 판매, 대치품
HIP6502
Absolute Maximum Ratings
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
DLA, DRV2. . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V12V +0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 5VSB + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3
Recommended Operating Conditions
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Digital Inputs, VSX, VEN5VDL,
Ambient Temperature Range .
VMSEL
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0 to +5.25V
0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 125oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX
VCC SUPPLY CURRENT
Nominal Supply Current
I5VSB
Shutdown Supply Current
I5VSB(OFF) VSS = 0.8V
POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS
- 30 -
- 14 -
Rising 5VSB POR Threshold
- - 4.5
5VSB POR Hysteresis
- 0.2 -
Rising 12V Threshold
- - 10.2
12V Hysteresis
- 1.0 -
Rising 3V3 and 5V Thresholds
- 90 -
3V3 and 5V Hysteresis
-5-
Soft-Start Current
Shutdown Voltage Threshold
3.3VMEM LINEAR REGULATOR (VOUT1)
Regulation
ISS
VSD
- 10 -
- - 0.8
- - 2.0
VSEN1 Nominal Voltage Level
VSEN1 Undervoltage Rising Threshold
VVSEN1 MSEL > 1.8V
- 3.3 -
- 2.77 -
VSEN1 Undervoltage Hysteresis
- 110 -
VSEN1 Output Current
2.5VMEM LINEAR REGULATOR (VOUT2)
Regulation
IVSEN1 5VSB = 5V
250 300
-
- - 2.0
VSEN2 Nominal Voltage Level
VSEN2 Undervoltage Rising Threshold
VVSEN2 MSEL < 2.0V
- 2.5 -
- 2.075 -
VSEN2 Output Current
IVSEN2
DRV2 Output Drive Current
IDRV2
3.3VDUAL/3.3VSB LINEAR REGULATOR (VOUT3)
Sleep State Regulation
5VSB = 5V
5VSB = 5V
250 300
220 -
-
-
- - 2.0
3V3DL Nominal Voltage Level
V3V3DL
- 3.3 -
UNITS
mA
mA
V
V
V
V
%
%
µA
V
%
V
V
mV
mA
%
V
V
mA
mA
%
V
4

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HIP6502CB 전자부품, 판매, 대치품
HIP6502
5VDLSB (Pin 14)
Connect this pin to the gate of a suitable P-MOSFET or
bipolar PNP. In sleep state, this transistor is switched on,
connecting the ATX 5VSB output to the 5VDUAL regulator
output.
VSEN1 (Pin 3)
Connect this pin to the 3.3V memory output (VOUT1). In
sleep states, this pin is regulated to 3.3V through an internal
pass transistor capable of delivering 300mA (typically). The
active-state voltage at this pin is provided from the ATX 3.3V
through a fully on external N-MOS transistor. During all
operating states, the voltage at this pin is monitored for
under-voltage events.
VCLK (Pin 6)
This pin is the output of the internal 2.5V clock chip regulator
(VOUT4). This internal regulator operates only in active
states (S0, S1/S2) and is shut off during any sleep state,
regardless of the configuration of the chip. This pin is
monitored for under-voltage events.
Description
Operation
The HIP6502 controls 5 output voltages (Refer to Figures 1,
2, and 3). It is designed for microprocessor computer
applications with 3.3V, 5V, 5VSB, and 12V bias input from an
ATX power supply. The IC is composed of three linear
controllers/regulators supplying the computer system’s
3.3VSB and PCI slots’ 3.3VAUX power (VOUT3), the 2.5V
RDRAM and 3.3V SDRAM memory power (VOUT2, VOUT1),
an integrated regulator dedicated to 2.5V clock chip
(VOUT4), a dual switch controller supplying the 5VDUAL
voltage (VOUT5), as well as all the control and monitoring
functions necessary for complete ACPI implementation.
Initialization
The HIP6502 automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5VSB input supply voltage, initiating 3.3VSB
soft-start operation after exceeding POR threshold. At 3ms
(typically) after 3.3VSB finishes its ramp-up, the EN5VDL
status is latched in and the chip proceeds to ramp up the
remainder of the voltages, as required.
Operational Truth Table
The EN5VDL pin offers the choice of supporting or disabling
5VDUAL output in S3 and S4/S5 sleep states. Table 1
describes the truth combinations pertaining to this output.
Not shown in any of the tables are the 3.3VDUAL/3.3VSB and
the 2.5VCLK outputs. The 3.3VDUAL/3.3VSB output powers
up as soon as the 5VSB ATX output is available. The
2.5VCLK output operation is restricted by the chip’s POR and
is only available in active state (S0, S1). For additional
information, see the soft-start sequence diagrams.
Additionally, the internal circuitry does not allow the
transition from an S3 (suspend to RAM) state to an S4/S5
(suspend to disk/soft off) state or vice versa. The only ‘legal’
transitions are from an active state (S0, S1) to a sleep state
(S3, S5) and vice versa.
TABLE 1. 5VDUAL OUTPUT (VOUT5) TRUTH TABLE
EN5VDL S5 S3 5VDL
COMMENTS
0
11
5V S0, S1 States (Active)
0
10
0V S3
0
01
Note Maintains Previous State
0
00
0V S4/S5
1
11
5V S0, S1 States (Active)
1
10
5V S3
1
01
Note Maintains Previous State
1
00
5V S4/S5
NOTE: Combination Not Allowed.
Functional Timing Diagrams
Figures 4 through 6 are timing diagrams, detailing the power
up/down sequences of all three outputs in response to the
status of the enable (EN5VDL) and sleep-state pins (S3,
S5), as well as the status of the ATX supply.
5VSB
S3
S5
3.3V,
5V, 12V
3V3DLSB
DLA
3V3DL
5VDLSB
5VDL
FIGURE 4. 5VDUAL TIMING DIAGRAM FOR EN5VDL = 1;
3.3VDUAL/3.3VSB
The status of the EN5VDL pin can only be changed while in
active (S0, S1) states, when the bias supply (5VSB pin) is
below POR level, or during chip shutdown (SS pin shorted to
GND or within 3ms of 5VSB POR); a status change of this
pin while in a sleep state is ignored.
7

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부품번호상세설명 및 기능제조사
HIP6502CB

Multiple Linear Power Controller with ACPI Control Interface

Intersil Corporation
Intersil Corporation

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