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PDF HIP6503 Data sheet ( Hoja de datos )
| Número de pieza | HIP6503 | |
| Descripción | Multiple Linear Power Controller with ACPI Control Interface | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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TM
Data Sheet
HIP6503
June 2000 File Number 4882.1
Multiple Linear Power Controller with
ACPI Control Interface
The HIP6503 complements either an HIP6020 or an
HIP6021 in ACPI-compliant designs for microprocessor and
computer applications. The IC integrates four linear
controllers/regulators, switching, monitoring and control
functions into a 20 pin SOIC package. One linear controller
generates the 3.3VDUAL/3.3VSB voltage plane from the ATX
supply’s 5VSB output, powering the south bridge and the
PCI slots through an external pass transistor during sleep
states (S3, S4/S5). A second transistor is used to switch in
the ATX 3.3V output for operation during S0 and S1/S2
(active) operating states. A linear controllers/regulator
supplies at choice either of 2.5V or 3.3V memory power
through external pass transistors (switch for 3.3V setting) in
active states. During sleep states, integrated pass
transistors supply the sleep power. Another controller
powers up the 5VDUAL plane by switching in the ATX 5V
output in active states, and the ATX 5VSB in sleep states.
Two internal regulators output both a dedicated, noise-free
2.5V clock chip supply, as well as a 1.8V ICH2 resume well
voltage. The HIP6503’s operating mode (active outputs or
sleep outputs) is selectable through two digital control pins,
S3 and S5. Enabling sleep state support on the 5VDUAL
output is offered through the EN5VDL pin. In active state, the
3.3VDUAL/3.3VSB and 2.5VMEM/3.3VMEM linear regulators
use external N-channel pass MOSFETs to connect the
outputs directly to the 3.3V input supplied by an ATX power
supply, for minimal losses. In sleep state, power delivery on
both outputs is transferred to NPN transistors - external to
the controller on the 3.3VDUAL/3.3VSB, internal on the
2.5VMEM/3.3VMEM. Active state regulation on the 2.5VMEM
output is performed through an external NPN transistor. The
5VDUAL output is powered through two external MOS
transistors. In sleep states, a PMOS (or PNP) transistor
conducts the current from the ATX 5VSB output; while in
active state, current flow is transferred to an NMOS
transistor connected to the ATX 5V output. The operation of
the 5VDUAL output is dictated not only by the status of the
S3 and S5 pins, but that of the EN5VDL pin as well. The
3.3VDUAL/3.3VSB and 1.8VSB outputs are active for as long
as the ATX 5VSB voltage is applied to the chip. The 2.5VCLK
output is only active during S0 and S1/S2, and uses the 3V3
pin as input source for its internal pass element.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HIP6503CB
0 to 70 20 Ld SOIC
HIP6503EVAL1 Evaluation Board
PKG.
NO.
M20.3
Features
• Provides 5 ACPI-Controlled Voltages
- 5VDUAL USB/Keyboard/Mouse (Active/Sleep)
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN (Active/Sleep)
- 2.5VMEM RDRAM or 3.3VMEM SDRAM (Active/Sleep)
- 2.5VCLK Clock/Processor Terminations (Active Only)
- 1.8VSB ICH2 Resume
• Excellent Output Voltage Regulation
- 3.3VDUAL/3.3VSB Output: ±2.0% Over Temperature;
Sleep State Only
- 2.5VMEM/3.3VMEM Output: ±2.0% Over Temperature;
Both Operational States (3.3VMEM in sleep only)
- 1.8VSB, 2.5VCLK Outputs: ±2.0% Over Temperature
• Small Size
- Very Low External Component Count
• Dual Memory Voltage Selection Via FAULT/MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
• Undervoltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
Applications
• Motherboard Power Regulation for ACPI-Compliant
Computers
Pinout
HIP6503
(SOIC)
TOP VIEW
5VSB 1
1V8IN 2
1V8SB 3
3V3DLSB 4
3V3DL 5
VCLK 6
3V3 7
EN5VDL 8
S3 9
S5 10
20 VSEN2
19 DRV2
18 5V
17 12V
16 SS
15 5VDL
14 5VDLSB
13 DLA
12 FAULT/MSEL
11 GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1 page  
HIP6503
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued)
PARAMETER (Note 2)
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
DRV2 Output Drive Current
DRV2 Output Impedance
IDRV2
3.3VDUAL/3.3VSB LINEAR REGULATOR (VOUT3)
Sleep State Regulation
5VSB = 5V, RSEL = 1kΩ
RSEL = 10kΩ
220 -
- 200
-
-
mA
Ω
- - 2.0 %
3V3DL Nominal Voltage Level
3V3DL Undervoltage Rising Threshold
V3V3DL
- 3.3 -
- 2.739 -
V
V
3V3DL Undervoltage Hysteresis
- 99 -
mV
3V3DLSB Output Drive Current
DLA Output Impedance
I3V3DLSB 5VSB = 5V
5 10 -
- 90 -
mA
Ω
2.5VCLK LINEAR REGULATOR (VOUT4)
Regulation
- - 2.0 %
VCLK Nominal Voltage Level
VCLK Undervoltage Rising Threshold
VVCLK
- 2.5 -
- 2.075 -
V
V
VCLK Undervoltage Hysteresis
- 75 -
mV
VCLK Output Current (Note 4)
5VDUAL SWITCH CONTROLLER (VOUT5)
5VDL Undervoltage Rising Threshold
IVCLK V3V3 = 3.3V
500 800
-
- 4.150 -
mA
V
5VDL Undervoltage Hysteresis
- 150 -
mV
5VDLSB Output Drive Current
5VDLSB Pull-Up Impedance to 5VSB
I5VDLSB 5VDLSB = 4V, 5VSB = 5V
-20 - -40
- 350 -
mA
Ω
TIMING INTERVALS
Active State Assessment Past Input UV
Thresholds (Note 5)
20 25 30
ms
Active-to-Sleep Control Input Delay
- 200 -
µs
CONTROL I/O (S3, S5, EN5VDL, FAULT/MSEL)
High Level Input Threshold
- - 2.2 V
Low Level Input Threshold
0.8 -
-
V
S3, S5 Internal Pull-up Impedance to 5VSB
- 50 -
kΩ
FAULT Output Impedance
FAULT = high
- 100 -
Ω
TEMPERATURE MONITOR
Fault-Level Threshold (Note 6)
Shutdown-Level Threshold (Note 6)
125 -
- 155
-
-
oC
oC
NOTES:
2. Sleep-State Only for 3.3V Setting
3. Parameters not guaranteed for 5VSB < 4.0V.
4. At Ambient Temperatures Less Than 50oC.
5. Guaranteed by Correlation.
6. Guaranteed by Design.
5
5 Page 
HIP6503
high-frequency decoupling capacitors should be placed as
close as possible to the load they are decoupling; the ones
decoupling the controller close to the controller pins, the
ones decoupling the load close to the load connector or the
load itself (if embedded). Even though bulk capacitance
(aluminum electrolytics or tantalum capacitors) placement is
not as critical as the high-frequency capacitor placement,
having these capacitors close to the load they serve is
preferable.
The critical small signal components include the soft-start
capacitor, CSS, as well as the memory selection resistor,
RSEL. Locate these components close to the respective pins
of the control IC, and connect them to ground through a via
placed close to the ground pad. Minimize any leakage
current paths from these nodes, since the internal current
sources are only 10s of microamperes (10µA to 40µA).
+12VIN
+5VSB
CHF1
CSS
CBULK1
VOUT1
C12V
12V
SS
C5VSB
5VSB
5VDLSB
5VDL
CIN
VOUT5
Q4
1V8SB
CBULK5
CHF5
Q2
CHF3
VOUT3
CBULK3
3V3DLSB
HIP6503
1V8IN
3V3DL
DLA
5V
Q3
CBULK4
VCLK
VSEN2
3V3 GND DRV2
Q5
+5VIN
VOUT2 CHF2
Q1 CBULK2
CHF4
+3.3VIN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT/POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 10. PRINTED CIRCUIT BOARD ISLANDS
A multi-layer printed circuit board is recommended. Figure
10 shows the connections of most of the components in the
converter. Note that the individual capacitors shown each
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections through vias placed as close
to the component terminal as possible. Dedicate another
solid layer as a power plane and break this plane into
smaller islands of common voltage levels. Ideally, the power
plane should support both the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers to create power islands connecting the filtering
components (output capacitors) and the loads. Use the
remaining printed circuit layers for small signal wiring.
Component Selection Guidelines
Output Capacitors Selection
The output capacitors for all outputs should be selected to
allow the output voltage to meet the dynamic regulation
requirements of active state operation (S0, S1). The load
transient for the various microprocessor system’s
components may require high quality capacitors to supply
the high slew rate (di/dt) current demands. Thus, it is
recommended that the output capacitors be selected for
transient load regulation, paying attention to their parasitic
components (ESR, ESL).
Also, during the transition between active and sleep states,
there is a short interval of time during which none of the
power pass elements are conducting - during this time the
output capacitors have to supply all the output current. The
output voltage drop during this brief period of time can be
easily approximated with the following formula:
∆V O U T
=
IOUT
×
E
S
RO
U
T
+
C-----O--t--t-U----T-
, where
∆VOUT - output voltage drop
ESROUT - output capacitor bank ESR
IOUT - output current during transition
COUT - output capacitor bank capacitance
tt - active-to-sleep or sleep-to-active transition time (10µs typ.)
The output voltage drop is heavily dependent on the ESR
(equivalent series resistance) of the output capacitor bank,
the choice of capacitors should be such as to maintain the
output voltage above the lowest allowable regulation level.
VCLK (VOUT4) Output Capacitors Selection
The output capacitor for the VCLK linear regulator provides
loop stability. Figure 11 outlines a capacitance vs. equivalent
series resistance envelope. For stable operation and
optimized performance, select a COUT4 capacitor or
combination of capacitors with characteristics within the
shown envelope.
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HIP6503.PDF ] | |
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