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부품번호 HIP7010 기능
기능 J1850 Byte Level Interface Circuit
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HIP7010 데이터시트, 핀배열, 회로
HIP7010
ADVANCE INFORMATION
August 1996
J1850 Byte Level Interface Circuit
Features
• Fully Supports VPW (Variable Pulse Width) Messaging
Practices of SAE J1850 Standard for Class B Data
Communications Network Interface
- 3-Wire, High-Speed, Synchronous, Serial Interface
• Reduces Wiring Overhead
• Directly Interfaces with 68HC05 and 68HC11 Style SPI
Ports
• 1MHz, 8-Bit Transfers Between Host and HIP7010
Minimize Host Service Requirements
• Automatically Transmits Properly Framed Messages
• Prepends SOF to First Byte and Appends CRC to Last
Byte
• Fail-Safe Design Including, Slow Clock Detection
Circuitry, Prevents J1850 Bus Lockup Due to System
Errors or Loss of Input Clock
• Automatic Collision Detection
• End of Data (EOD), Break, Idle Bus, and Invalid Symbol
(Noise/Illegal Symbols) Detection
• Supports In-Frame Responses with Generation of
Normalization Bits (NB) for Type 1, Type 2, and Type 3
Messages
• Wait-For-Idle Mode Reduces Host Overhead During
Non-Applicable Messages
• Status Register Flags Provide Information on Current
Status of J1850 Bus
• Serial I/O Pins are Active Only During Transfers - Bus
Available for Other Devices 95% of the Time
• TEST Pin Provides Built-in-Test Capabilities for
In-System Diagnostics and Factory Testing
• High Speed (4X) Receive Mode for Production and
Diagnostic Testing/Programming
• Operates with Wide Range of Input Clock Frequencies
• Power-Saving Power-Down Mode
• Full -40oC to +125oC Operating Range
• Single 3.0V to 6.0V Supply
Description
The Intersil HIP7010, J1850 Byte Level Interface Circuit, is a
member of the Intersil family of low-cost multiplexed wiring
ICs. The integrated functions of the HIP7010 provide the
system designer with components key to building a “Class B”
multiplexed communications network interface, which fully
conforms to the VPW Multiplexed Wiring protocol specified
in the SAE J1850 Standard. The HIP7010 is designed to
interface with a wide variety of Host microcontrollers via a
standard three wire, high-speed (1MHz), synchronous, serial
interface. The HIP7010 automatically produces properly
framed VPW messages, prepending the Start of Frame
(SOF) symbol and calculating and appending the CRC
check byte. All circuitry needed to decode incoming mes-
sages, to validate CRC bytes, and to detect Breaks, End of
Data (EOD), Idle bus, and illegal symbols is included. In-
Frame Responses (IFRs) are fully supported for Type 1,
Type 2, and Type 3 messages, with the appropriate Normal-
ization Bit automatically generated. The HCMOS design
allows proper opeSration at various input frequencies from
2MHz to 12MHz. Connection to the J1850 Bus is via a Inter-
sil HIP7020.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG. NO.
HIP7010P
-40 +125 14 Lead Plastic DIP
E14.3
HIP7010B
-40 +125 14 Lead Plastic SOIC (N) M14.15
Pinout
HIP7010 (SOIC, PDIP)
TOP VIEW
IDLE 1
VPWIN 2
VPWOUT 3
VDD 4
RESET 5
TEST 6
SACTIVE 7
14 RDY
13 STAT
12 CLK
11 VSS
10 SIN
9 SOUT
8 SCK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 3644.2




HIP7010 pdf, 반도체, 판매, 대치품
HIP7010
Serial Interface Timing (See Figure 1- Figure 7) TA = -40oC to +125oC, VDD = 5VDC ±10%, Unless Otherwise Specified
NUMBER SYMBOL
PARAMETERS
MIN TYP MAX UNITS
- - Operating Frequency
2 8 12 MHz
- - Input CLK Duty Cycle
40 50 60 %
(1) tCYC SCK Cycle Time
(2) tLEAD SACTIVE Lead Time
Before Status/Control Transfer
- 1.0 - MHz
450 750 850
ns
Before Data Transfer
1150 1225 1300
ns
(3)
tLAG
SACTIVE Lag Time
After Status/Control Transfer
650 750 850
ns
After Data Transfer
1250 1300 1400
ns
(4) tSCKH Clock (SCK) HIGH Time
450 500 550
ns
(5) tSCKL Clock (SCK) LOW Time
450 500 550
ns
(6) tDVSCK Required Data In Setup Time (SIN to SCK)
- 10 50 ns
(7) tSCKDX Required Data In Hold Time (SIN after SCK)
-
-10 40
ns
(8)
tDZDA Data Active from High Impedance Delay (SACTIVE to SOUT Active) -10
10
-
ns
(9) tDADZ Data Active to High Impedance Delay (SACTIVE to SOUT High
Impedance)
- 10 40 ns
(10) tDVSCK Data Out Setup Time (SOUT to SCK)
(11) tDXSCK Data Out Hold Time (SOUT after SCK)
(12) tRISE Output Rise Time (0.3VDD to 0.7VDD, CL = 100pF)
(13) tFALL Output Fall Time (0.7VDD to 0.3VDD, CL = 100pF)
(14) tSTATH Required STAT Pulse Width
(15) tRDYH Required RDY Pulse Width
tRESETL Required RESET Pulse Width
(16) tSACTIVE SACTIVE Delay from RDY (IDLE = VSS)
SACTIVE Delay from STAT (FTU = 0)
375
375
15
7
-
-
-
1150
5
475
475
75
25
20
20
20
1750
285
-
-
150
75
75
75
75
2450
900
ns
ns
ns
ns
ns
ns
ns
ns
ns
(17) tRDYSCK Required RDY Removal Time Prior to Last SCK for Short RDY
(18) tSCKRDY Required RDY Hold Time after Last SCK for Long RDY
(19) tREC Required SERIAL Recovery Time (Minimum Time after SACTIVE
Until Next RDY/STAT)
- 25 100 ns
- 0 100 ns
-
675 750
ns
fSLOW Slow clock detect frequency limit
20 80 200 KHz
NOTE:
1. All parameters are specifications of the HIP7010 component not of a system. Parameters specified as “Required” (i.e., tSTATH) refer to
the requirements of the HIP7010. If a “Required” pulse width is specified as 75ns maximum, that implies that 75ns is the maximum width
that any HIP7010 device will require. Therefore, a system that provides a minimum pulse width of 75ns will satisfy this maximum
requirement.
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HIP7010 전자부품, 판매, 대치품
HIP7010
J1850 VPW Messaging
This section provides an introduction to J1850 multiplexed
communications. It is assumed that the user is or will
become familiar with the appropriate documents published
by the Society of Automotive Engineering (SAE). The follow-
ing discussion is not comprehensive.
Overview
The SAE J1850 Standard (Note 1) (J1850) establishes the
requirements for communications on a Class B multiplexed
wiring network for automotive applications. The J1850 docu-
ment details the requirements in a three layer description
which separately specifies the characteristics of the physical
layer, the data link layer, and the application layer. There are
several options within each layer which allows vehicle manu-
facturers to customize the network while still maintaining a
level of universality.
NOTE:
1. SAE J1850 Standard, Class B Data Communication Network
Interface, May 1994, Society of Automotive Engineers Inc.
The hardware of the Intersil HIP7010 provides features
which facilitate implementation of the 10.4Kbps Variable
Pulse Width Modulated (VPW) physical layer option of
J1850. In combination with a bus transceiver, such as the
Intersil J1850 Bus Transceiver HIP7020, and appropriate
software algorithms, the HIP7010 circuitry enables the
designer to completely implement a 10.4Kbps VPW Class B
Communications Network Interface per J1850. Features of
such an implementation include:
• Single Wire 10.4Kbps Communications
• Bit-by-Bit Bus Arbitration
• Industry Standard Protocol
• Message Acknowledgment (“In-Frame Response”) Capa-
bilities
• Exceptionally Tolerant of Clock Skew, System Noise, and
Ground Offsets
• Meets CARB and EPA Diagnostic Requirements
• Supports up to 32 Nodes
• Low Error Rates
• Excellent EMC Levels (when interfaced via Intersil J1850
Bus Transceiver HIP7020)
In addition to the standard J1850 features, the HIP7010 hard-
ware provides a high speed mode, (intended for receive only
use) which can significantly enhance vehicle maintenance
capabilities. The high speed mode provides a 41.6Kbps com-
munications path to any node built with the HIP7010.
Anatomy of a J1850 VPW Message
All messages in a J1850 VPW system are sent along a single
wire, shared bus. At any given moment the bus can be in
either of two states: active (high) or passive (low). Multiple
nodes are connected to the bus as a “wired-OR” network in
which the bus is high if any one (or more) node is generating
an active output. The bus is only low when no nodes are gen-
erating active outputs. It follows that, when no communica-
tions are taking place the bus will rest in the passive state. A
message begins when the bus is first driven to the high state.
Each succeeding state transition (i.e., a change from active to
passive or passive to active) transfers one bit of information
(symbol) until the message is complete and the bus once
again rests at the passive state. The interpretation of each
symbol in the message is dependent on its duration (and
state), hence, the descriptor Variable Pulse Width (VPW).
Each message has a beginning and an end, the span of
which encompasses the entire message or frame (refer to
Figure 3). A frame consists of an active start of frame (SOF)
symbol and a passive end of frame (EOF) symbol sandwiched
around a series of byte sized (8-bit) groups of symbols. The
first byte of the frame contents is always a header byte, fol-
lowed by possibly additional header bytes, followed by one or
more data bytes, followed by an integrity check byte (CRC
byte), followed by a passive end of data (EOD) symbol, fol-
lowed by possibly one or more in-frame-response (IFR) bytes.
To keep waiting times low, messages are limited to 12 bytes
total (including header, data, check, and IFR bytes). All mes-
sage bytes are transmitted most significant bit (MSB) first.
VPW Symbol Definitions
Within the J1850 scheme, symbols are defined in terms of both
duration and state (passive or active). The duration is mea-
sured as the time between successive transitions. There is one
transition per symbol and one symbol per transition. The end of
one symbol marks the beginning of the next. Since the bus is
passive when a message begins and must return to that same
state when the message completes, all frames have an even
number of transitions and hence an even number of symbols.
There are unique definitions for data bit symbols (all the sym-
bols which occur within the header, data, and check bytes) and
protocol symbols (including SOF, EOD, and EOF). The duration
of each symbol is expressed in terms of VPW Timing Pulses
(TV values). Table 1 summarizes the TV definitions. Each TV is
specified in terms of a nominal (or ideal) duration and a mini-
mum and maximum duration. The span between the minimum
and maximum limits accommodates system noise sources
such as node to node clock skew, ground offsets, clock jitter,
and electromechanical noise. There are no dead zones
between the maximum of one TV and the minimum of the next.
SOF
HEADER
DATA 1
DATA 2
CRC
FIGURE 3. TYPICAL J1850 VPW MESSAGE FRAME
EOD
EOF
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