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PDF HIP7020AP Data sheet ( Hoja de datos )
| Número de pieza | HIP7020AP | |
| Descripción | J1850 Bus Transceiver For Multiplex Wiring Systems | |
| Fabricantes | Intersil Corporation | |
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HIP7020
June 1998
J1850 Bus Transceiver
For Multiplex Wiring Systems
Features
Description
• J1850 Bus Transceiver for MX Wiring
• 5V CMOS/TTL Logic Interface
• Current Controlled Transmitter Driver
• Controlled Rise/Fall Time of Bus Drive for Both
Voltage and Current
• Bus Drive Capability to Less Than 500Ω with a 5µs
Load RC Time Constant
• Filtered Bus Input Receiver
• Ground Fault Tolerant for Bus Isolation
• Short Circuit and Over Temperature Protection
• Protection for Reverse Battery, Load Dump
and Latch-Up
• ±9kV ESD Protection BUS OUT and BATTERY Pins
• -40oC to 125oC Operating Range
• Loop-Back Fault Detection Mode
• 4x (41.6kHz) Receive Speed
Ordering Information
PART
NUMBER
HIP7020AB
HIP7020AP
TEMP.
RANGE (oC)
PACKAGE PKG. NO.
-40 to 125 8 Ld SOIC
M8.15
-40 to 125 8 Ld PDIP
E8.3
The HIP7020 IC is an Integrated I/O Bus Transceiver
designed for the SAE Standard J1850 Class B Data Com-
munication Network Interface. The Bus transmits and
receives data on a single wire using a 10.4kHz VPWM (Vari-
able Pulse Width Modulated) signal. The HIP7020 serves as
an I/O buffer interfacing to 5V CMOS logic. It is designed to
operate directly from the 12V battery line of an automobile.
The normal Bus voltage swing capability is from 0V to 7.75V
at currents greater than 20mA.
As shown in the Block Diagram, the Transmitter TX Input and
the Receiver RX Output of the Bus Transceiver Circuit inter-
face to the control logic. The TX input signal is wave shaped
for rise time, fall time and amplitude before it is converted
from voltage to current. The Wave Shaper with an external
programming resistor, RS controls the rise and fall time of
the BUS OUT output signal. The current source drive to the
Bus is voltage controlled by the Wave Shaped Voltage Refer-
ence to a maximum limit as specified for the J1850 Bus and
includes short-circuit current limiting.
The HIP7020 Receiver input, BUS IN is connected to the
J1850 Bus through an external resistor, RF and has a trip
point at one-half of the nominal Bus signal voltage which is
3.875V. The Receiver input is filtered to remove high fre-
quency Bus noise by the external resistor and an internal
capacitor. The Receiver Bus signal, after processing, is out-
put at the RX pin by the RX Buffer’s open collector driver.
The RX output is active low and requires an external pull-up
resistor returned to the control logic VCC supply. This pre-
vents power-up of the control logic by the transceiver if VCC
supply voltage is removed.
The HIP7020 has a Loop-Back Enable Mode Switch to
return diagnostic information for the Bus Transceiver node.
For an active low or an open LB EN input, the Trans-
mit/Receive signals are internally “Looped-Back” to provide
a TX to RX return signal path independent of signals on the
Bus. A return path validation indicates proper action of the
Bus Transceiver apart from the J1850 Bus.
Pinout
HIP7020
(PDIP, SOIC)
TOP VIEW
BATT 1
TX 2
R/F TIME 3
RX 4
8 GND
7 BUS OUT
6 LB EN
5 BUS IN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 3642.3
1 page  
HIP7020
Test Circuits
VBATT
510 0.1µF
100
0.1µF
TX BATT
LB EN
10K RX R/F
BUS OUT
10
BUS IN
GND
15K
5.1V
56.2K ±1%
SW
µA
500
FIGURE 3. LOSS OF GROUND LEAKAGE TEST CIRCUIT
0.01µF
VTX LOW = 0V
VTX HIGH = 5V
TX
TRANSMIT WAVEFORM
PROCESSING/SHAPING
ISTX
R/F
RS
56.2K ±1%
LB EN
5V
RD
5K
RX
VREF
GND
DIAGNOSTIC
LOOP-BACK
MODE SW †
† SWITCH SHOWN
ISLB IN NORMAL MODE
BUS RECEIVER AND
VOLTAGE COMPARATOR
VBATT
BATT
VOLTAGE TO
CURRENT
CONVERTER
Q1
FILTER
BUS OUT
RE IBO
VBO
10 RBS
CBS
RF
15K
BUS IN
RBS = 500Ω TO 1500Ω
τ = RBSCBS ≅ 5µs
FIGURE 4. ELECTRICAL SPECIFICATION TEST CIRCUIT
HIP7020 Signal Interface
The HIP7020 is a member of the Intersil family of low cost
multiplexed wiring ICs. As a Bus Transceiver IC, it interfaces
the module and system control logic to the vehicle signal bus
wiring. The integrated functions of the Bus Transceiver serve
as an interface for a “Class B” multiplexed communications
network. The TX digital interface is designed to accept
CMOS/TTL logic levels and convert them to the appropriate
J1850 analog serial data levels. This is accomplished using
an internally generated reference waveform and voltage
driver with a controlled current source to supply an analog
signal output to the J1850 bus load of 500Ω (typical).
Because of the special wave shaping used to control the
J1850 bus waveform, it is regarded as an analog signal.
In the receive mode the incoming bus analog signals are input
to the receiver at the BUS IN terminal. The bus data is
converted to logic information by comparing it to an on-chip
reference voltage. The received signal is provided as digital
output from an open collector transistor driver at the
RX output.
In the transmit mode a CMOS/TTL digital signal is received
at the TX input. It is then rise and fall time controlled, wave
shaped and level adjusted. A voltage controlled current
driver circuit transmits the signal from the BUS OUT terminal
to the J1850 Bus with current limiting protection.
Functional Blocks
The Bus Transceiver IC functional blocks, as shown in the
Block Diagram, are as follows:
TX BUF (Transmit Input Buffer Interface)
The TX Buffer input function is a data interface to the wave-
shaper reference circuit. The CMOS/TTL logic levels to be
transmitted are input to the TX pin.
5
5 Page 
HIP7020
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
E
-B-
H
0.25(0.010) M B M
123
-A-
D
SEATING PLANE
A
L
h x 45o
-C-
e A1
B
0.25(0.010) M C A M B S
α
0.10(0.004)
C
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.0532 0.0688 1.35
1.75
-
A1
0.0040 0.0098 0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075 0.0098 0.19
0.25
-
D
0.1890 0.1968 4.80
5.00
3
E
0.1497 0.1574 3.80
4.00
4
e 0.050 BSC
1.27 BSC
-
H
0.2284 0.2440 5.80
6.20
-
h
0.0099 0.0196 0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N8
87
α 0o 8o 0o 8o -
Rev. 0 12/93
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
11
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet HIP7020AP.PDF ] | |
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