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PDF HIP7030A2M Data sheet ( Hoja de datos )
| Número de pieza | HIP7030A2M | |
| Descripción | J1850 8-Bit 68HC05 Microcontroller | |
| Fabricantes | Intersil Corporation | |
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HIP7030A2
ADVANCE INFORMATION
August 1996
J1850 8-Bit 68HC05 Microcontroller
Features
• Fully Supports VPW Specifications of SAE J1850
Standard for Class B Data Communications Network
Interface
• On-Chip Memory
• 176 Bytes of RAM
• 2110 Bytes of User ROM
• 13 Bidirectional I/O Lines
• 16-Bit Timer with Capture and Compare Registers
• Serial Peripheral Interface (SPI) System
• Watchdog Timer and Slow Clock Detect
• 10MHz Operating Frequency (5.0MHz Internal Bus
Frequency) at 5V
• Built-In-Test Bootstrap Mode with 242 Bytes of ROM
• Two Channel Analog Comparator
• On-Chip Oscillator Amplifier
• 8-Bit CPU Architecture
• Power-Saving STOP, WAIT and Data Retention Modes
• Full -40oC to 125oC Operating Range
• Single 3.0V to 6.0V Supply
• 28 Lead Dual-In-Line and Small Outline Plastic Pack-
ages
Software Features
• Standard 68HC05 Instruction Set
• True Bit Manipulation
• Addressing Modes Include Indexed Addressing
- Memory Mapped I/O
Ordering Information
PART NUMBER
HIP7030A2P
HIP7030A2M
TEMP.
RANGE (oC)
PACKAGE
-40 to 125 28 Lead Plastic
DIP
-40 to 125 28 Lead Plastic
SOIC (W)
PKG.
NO.
M28.3
E28.6
Description
The HIP7030A2 HCMOS Microcomputer is a member of the
CDP68HC05 family of low-cost single-chip microcomputers.
The integrated hardware functions provide the system
designer with a complete set of building blocks for
implementing a “Class B” multiplexed communications net-
work interface, which fully conforms to the VPW Multiplexed
Wiring protocol specified in SAE Recommended Practice
J1850. This 8-bit microcomputer unit (MCU) contains an on-
chip oscillator, CPU, 176 bytes of RAM, 2110 bytes of user
ROM, 13 I/O lines, a J1850 Variable Pulse Width Symbol
Encoder/Decoder (VPW SENDEC) system, a Serial Periph-
eral Interface (SPI) system, a two channel analog Compara-
tor, a Watchdog Timer, a Slow Clock Detect, and a 16-bit
Timer. The static HCMOS design allows operation at input
frequencies up to 10MHz (5MHz internal clock).
Table of Contents
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Electrical & Timing Specifications . . . . . . . . . . . . . . . . . . . . . 3
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Integrated Hardware I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Built-In Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Programmable Timer
Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . 27
J1850 VPW Messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Symbol Encoder Decoder
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
COP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Effects of STOP and WAIT Modes . . . . . . . . . . . . . . . . . . . . 41
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Package Outline Dimensions . . . . . . . . . . . . . . . . . . . . 55 - 56
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
I/O, Control, Status and Data Register Definitions . . . . . . . 52
Ordering
Information Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 3646.2
1 page  
HIP7030A2
Serial Peripheral Interface (SPI) Timing (See Figure 3) VDD = 5VDC ±10%, VSS = 0VDC, TA = -40oC to 125oC
Unless Otherwise Specified
NUMBER
PARAMETER
SYMBOL
MIN
MAX
UNITS
Operating Frequency
Master
fOP(M)
0.03
0.5 fOP
(Note 3)
1
2
3
4
5
6
7
8
9
10
11
12
13
NOTES:
Slave
Cycle Time
Master
Slave
Enable Lead Time
Master
Slave
Enable Lag Time
Master
Slave
Clock (SCK) High Time
Master
Slave
Clock (SCK) Low Time
Master
Slave
Data Setup Time (Inputs)
Master
Slave
Data Hold Time (Inputs)
Master
Slave
Access Time (Time to Data Active from High Impedance State)
Slave
Disable Time (Hold Time to High Impedance State)
Slave
Data Valid Time
Master (Before Capture Edge)
Slave (After Enable Edge) (Note 2)
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
Rise Time (VDD = 20% to 70%, CL = 100pF)
SPI Outputs (SCK, MOSI, MISO)
SPI Inputs (SCK, MOSI, MISO, SS)
Fall Time (VDD = 20% to 70%, CL = 100pF)
SPI Outputs (SCK, MOSI, MISO)
SPI Inputs (SCK, MOSI,MISO, SS)
fOP(S)
DC
tCYC(M)
tCYC(S)
2
200
tLEAD(M)
tLEAD(S)
(Note 1)
50
tLAG(M)
tLAG(S)
(Note 1)
50
tW(SCKH)M
tW(SCKH)S
200
50
tW(SCKL)M
tW(SCKL)S
200
50
tSU(M)
tSU(S)
50
50
tH(M)
tH(S)
50
50
tA 0
tDIS -
tV(M)
tV(S)
0.25
-
tHO(M)
tHO(S)
0.25
0
tR(M)
tR(S)
-
-
tF(M)
tF(S)
-
-
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
120
200
-
150
-
-
50
2
50
2
MHz
tCYC
ns
-
ns
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCYC(M)
ns
tCYC(M)
ns
ns
µs
ns
µs
1. Signal Production depends on software.
2. Assumes 200pF load on all SPI pins.
3. Note that the units this specification uses is fOP (internal operating frequency), not MHz! In the master mode the SPI bus is capable of
running at one-half of the devices’s internal operating frequency, therefore, 2.5MHz maximum.
5
5 Page 
HIP7030A2
All Port D I/Os are configured as inputs during a POR, COP,
or external reset. Refer to PD0-PD4 Special Function I/O
Lines under Port A and D I/O Lines for a detailed description
of programming the Port D I/O lines.
VPWOUT (Variable Pulse Width Out - Output),
VPWIN (Variable Pulse Width In - Input)
These two lines are used to interface to the J1850 bus trans-
ceiver.
VPWOUT is the pulse width modulated output of the SEN-
DEC encoder block.
VPWIN is the inverted input to the SENDEC decoder block.
See VPW Symbol Encoder/Decoder (SENDEC) for a
detailed description of the J1850 interface pins.
MISO (Master-in/Slave-out - Input/Output),
MOSI (Master-out/Slave-in - Input/Output),
SCK (Serial Clock - Input/Output),
SS (Slave Select - Input)
These four lines constitute the Serial Peripheral Interface
(SPI) communications port. The MCU can be configured as
a SPI “master” or as a SPI “slave”. In master mode MOSI
and SCK function as outputs and MISO functions as an
input. In slave mode MOSI and SCK are inputs and MISO is
an output. SS is always an input.
Serial data words are transmitted and received over the
MISO/MOSI lines synchronously with the SCK clock stream.
The word size is fixed at 8-bits. Single buffering is used
which results in an inherent inter-byte delay. The master
device always provides the synchronizing clock.
A low on the SS line causes the MCU to immediately
assume the role of slave, regardless of it’s current mode.
This allows multi-master systems to be constructed with
appropriate arbitration protocols.
See the detailed discussion of the SPI interface under Serial
Peripheral Interface (SPI).
Integrated Hardware I/O Functions
PORT A
Each of the Parallel Port pins of Port A may be individually
programmed as an input or an output under software control.
The direction of each pin is determined by the state of the
corresponding bit in the Port A Data Direction Register
(DDRA, location $04).
PORT DATA
PORT DRR
VDD
P
N
PAD
INTERNAL LOGIC
DATA
DIR REG
BIT
LATCHED
OUTPUT
DATA BIT
OUTPUT
I/O
PIN
INPUT REG BIT
INPUT I/O
FIGURE 5B. PORT A FUNCTIONAL BLOCK DIAGRAM
76543210
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
PORT A DATA DIRECTION REGISTER (DDRA, LOCATION $04)
Any Port A pin is configured as an output if its corresponding
DDR bit is set to a logic one. A pin is configured as an input if
its corresponding DDR bit is cleared to a logic zero. Any
reset will clear all DDR bits, which configures all Port A and
D pins as inputs. The data direction register is capable of
being written to or read by the processor. Refer to Figure 5
and Table 1.
76543210
A7 A6 A5 A4 A3 A2 A1 A0
PORT A DATA REGISTER (PORTA, LOCATION $00)
Port A is an 8-bit wide read-write data register. Regardless
of the state of the DDRA bits, all Port A data latches are
modified with each write to Port A. When Port A is read, the
value read for bits programmed as outputs, is the contents of
the data latch, not the pin. The value read for bits pro-
grammed as inputs is the value on the pin.
TABLE 1. PORT A TRUTH TABLE
(NOTE 1)
R/W
W
W
R
R
DDR
0
1
0
1
I/O PIN FUNCTION
The I/O pin is in input mode.
Data is written into the output data latch
Data is written into the output data latch
and simultaneously output to the I/O pin.
The state of the I/O pin is read.
The I/O pin is in output mode.
The output data latch is read.
NOTE:
1. R/W is an internal signal which equals R when reading the Port
Data Register and equals W when writing the Port Data Register.
PD0-PD4 SPECIAL FUNCTION I/O LINES
These five lines comprise Port D. The five lines can be indi-
vidually programmed to provide input or output capabilities
similar to the eight Port A lines. Additionally, each of the lines
FIGURE 5A. PORT A I/O PAD CIRCUITRY
11
11 Page | ||
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| PDF Descargar | [ Datasheet HIP7030A2M.PDF ] | |
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