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HIP9010 데이터시트 PDF




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부품번호 HIP9010 기능
기능 Engine Knock Signal Processor
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HIP9010 데이터시트, 핀배열, 회로
Data Sheet
HIP9010
November 1998 File Number 3601.4
Engine Knock Signal Processor
The HIP9010 is used to provide a method of detecting
premature detonation or “Knock” in automotive engines.
A block diagram of this IC is shown in Figure 1. The chip
alternately selects one of the two sensors mounted on the
engine block. Two programmable bandpass filters process
the signal from both sensors, and divides the signal into two
channels. When the engine is not knocking, programmable
gain adjust stages are set to ensure that both the reference
channel and the knock channel contain similar energies.
This technique ensures that the detection system is
comparatively immune to changes in the engine background
noise level. When the engine is knocking, the energy in the
knock channel increases.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HIP9010AB
-40 to 125 20 Ld SOIC (W)
PKG.
NO.
M20.3
Features
• Two Sensor Inputs
• Microprocessor Programmable
• Accurate and Stable Filter Elements
• Digitally Programmable Gain
• Digitally Programmable Time Constants
• Digitally Programmable Filter Characteristics
• On-Chip Clock
• Operating Temperature Range -40oC to 125oC
Applications
• Engine Knock Detector Processor
• Analog Signal Processing where Controllable Filter
Characteristics are Required
Pinout
HIP9010
(SOIC)
TOP VIEW
VDD
GND
VMID
INOUT
1
2
3
4
NC 5
NC 6
INT/HOLD 7
CS 8
OSCIN 9
OSCOUT 10
20 S0IN
19 S0FB
18 S1FB
17 S1IN
16 NC
15 NC
14 TEST
13 SCK
12 MOSI
11 MISO
4-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999




HIP9010 pdf, 반도체, 판매, 대치품
HIP9010
Electrical Specifications VDD = 5V, ±5%, GND = 0V, Clock Frequency 4MHz, ±0.5%, TA = -40oC to 125oC,
Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
INTEGRATOR
Integrator Offset Voltage
Integrator Reset Voltage
Integrator Droop after 500µs
OUTPUT AND SAMPLE AND HOLD
INTGVIO
VRESET
VDROOP
By Design
Pin 4 Voltage at Initiation of
Integration Cycle. VDD = 5V
Hold Mode, Pin 7 = 0V, VDD = 5V,
Pin 4 set to 20% to 80% of VDD
- 0.1 - mV
430 500 570 mV
- ±3 ±50 mV
Differential to Single Ended
Converter Offset Voltage
DIFVIO By Design
- 0.1 - mV
Change in Converter Output
DIFOUT Run Mode, 500µA, Sinking to No Load
-
±1 ±3 mV
SYSTEM GAIN DEVIATION
Gain Deviation from “Ideal Equation”
Correlation, Factor - 5.0%
VOUT -
VRESET
Run Mode, maximum signal output
from Input Amplifier <2.25VP-P,
Equation Output x 0.95 + Device
Reset Voltage. For Total VOUT 4.7V
-8%,
±100mV
Equation
x 0.95
-VRESET
8%,
±100mV
NOTE:
2. Q = fO/BW, Where: fO = Center Frequency, BW = 3dB bandwidth.
Ideal Equation
INTOUT(volts)
=
Input signal (VP P ) × R--R---I-F-N--
 G K
×
1.273
×
-T----C------(--m-----s---)---N-×----f--Q-------(--k---H----z---)
GR
×
1.273
×
T-----C------(--m-----s---)---N-×----f--Q-------(--k---H----z---)
+ VRESET
V
When the two filters are set to the same frequency and the input signal is present for the periods TIN, then:
INTOUT(volts) = Input signal (VP P ) × R--R---I-F-N-- 1.273 × -TT---I-C-N-- (GK GR) + VRESET
GR and GK = Programed Gain of Reference and Knock channels.
TIN = Time input signal is present In ms.
TC = Programmed integrator time constant ms.
N = Number of cycles of input signal.
fQ = Frequency of input signal. Assumes both filters are programmed to the same frequency.
VRESET = Integrator Reset Voltage.
1.273 = 4/π
RF = Feedback resistor value.
RIN = Signal input resistor value.
For example, assume 300mVP-P input with the time constant programmed to 300µs and the Integration time is 1.2ms. The RF/RIN ratio is one and
the Reference channel is programmed to a Gain of 0.188. The Knock channel is then automatically set to a gain of one. The input signal is contin-
uous for the total integration time, TIN.
INTOUT(volts) = 0.3V (VP P ) ×
1.273
×
0----.1--3-.--02---0-m---m--s----s-
×
( 1.000
0.188 )
+ VRESET = 1.24V + 0.500V = 1.74V
4-4

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HIP9010 전자부품, 판매, 대치품
HIP9010
Balance/Gain Adjust Stage
The gains from the Knock Frequency Filter and the
Reference Frequency Filter can be adjusted with respect to
one another, so that the difference energies in the two bands
can be compensated. This balance is achieved by feeding
one of the filters unattenuated (gain = 1) and attenuating the
other. This can be adjusted with 64 different gain settings,
ranging between 1 and 0.133. The signals can swing
between 20 and 80 percent of VDD.
Programming is discussed in the Communications Protocol
section. The test/channel attenuate word is used to
determine which of the two channels is attenuated and
which is set to unity gain.
Active Full Wave Rectifier
The output of the filters are independently full wave rectified
using switch capacitor techniques. Each of two rectifier
circuits provide both negative and positive values for the
knock frequency and reference frequency filter outputs. The
output is able to swing from 20% to 80% of VDD. Care was
taken to minimize the RMS variations from input to output of
this section.
Integrator Stage
The signals from the two rectifiers are summed and
integrated together. A differential system is used to reduce
noise. One system integrates the positive energy of the
Knock Frequency Rectifier with respect to the positive
energy of the Reference Frequency Rectifier. The second
system does the integration of the negative energy value of
the two rectifiers. The positive and negative energy signals
are opposite phase signals. Using this technique reduces
system noise.
The integrator time constant is software programmable by
the Integrator Time Constant discussed in the
Communications Protocol section. The time constant can be
programmed from 40µs to 600µs, with a total of 32 steps. If
for example, we program a time constant to 200µs, then with
one volt difference between each channel, the output of the
integrator will change by 1 volt in 200µs.
When integration is enabled by the rising edge of the
INT/HOLD input, the output of the integrator will fall to 0.5V,
within 20µs after the integrate line reaches the integrate
state. The output of the integrator is an analog voltage.
Test Multiplexer
This circuit receives the positive and negative outputs from
the two integrators, together with the outputs from different
parts of the IC. The output is controlled by the fifth
programming word of the communications protocol. This
multiplexes the switch capacitor filter output, the gain control
output and the antialiasing filter output.
Differential to Single-Ended Converter
This signal takes the output of the two integrators (through
the test-multiplexer circuit) and provides a signal that is the
sum of the two signals. This technique is used to improve the
noise immunity of the system.
Output Buffer
This output amplifier is the same amplifier circuits as the
input amplifier used to interface with the sensors. When the
output of the antialiasing filter is tested, this amplifier is in the
power down mode.
Communications Protocol
The multiprocessor talks to the knock sensor via an SPI
bus (MOSI). A chip select pin (CS) is used to enable the
chip, which, in conjunction with the SPI clock (SCK), moves
in the eight bit programming word. Five different
programming words are used to set gains, frequency
response, integrator constants, test mode, channel select
and test mode conditions.
With chip select (CS) going low, on the next rising edge of
the SPI clock (SCK), data is latched into the IC. The data is
shifted with the most significant bit first and least significant
bit last. Each word is divided into two parts: first the address
and then the value. Depending on the function being
controlled, the address is 2 or 3 bits, and the value is either 5
or 6 bits long. During the hold mode of operation, all five
programming words can be entered into the IC, but during
the integrate time any single byte may be entered but will not
be acted upon until the start of the next hold period. The
integration or hold mode of operation is controlled by the
INT/HOLD input signal.
Programming Words
1. Reference Filter Frequency: Defines the center frequency
of the Reference Filter in the system. The first 2 bits are
used for the address and the last 6 bits are used for its
value. 01FFFFFF Example: 01001010 would be the
reference filter (01 for the first two bits) at a center
frequency of 1.78kHz (bit value in Table 2 of 10).
2. Knock Filter Frequency: Defines the center frequency of
the Knock Filter in the system. The first 2 bits are used for
the address and the last 6 bits are used for its value.
00FFFFFF Example: 00100111 would be the knock filter
frequency (00 for the first two bits) at a center frequency
of 6.37kHz (bit value in Table 2 of 39).
3. Balance Control: Defines the ratio of the gain of the knock
band center frequency to that of the reference band
center frequency. This role can be reversed by the value
of CA in the fifth programming bit, as explained in 5,
Test/Channel Select/Channel Attenuate Control. The first
2 bits are used for the address and the last 6 bits for its
value. 10GGGGGG Example: 10010100 would be the
balance control (10 for the first two bits) with an
attenuation of 0.514 (bit value in Table 2 of 20.)
Depending on the value of CA in the fifth word this would
apply to the reference or the knock gain section.
4-7

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관련 데이터시트

부품번호상세설명 및 기능제조사
HIP9010

Engine Knock Signal Processor

Intersil Corporation
Intersil Corporation
HIP9010AB

Engine Knock Signal Processor

Intersil Corporation
Intersil Corporation

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