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기능 (PKS603 - PKS607) Off-Line Switcher IC
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PKS604P 데이터시트, 핀배열, 회로
PKS603-607
PeakSwitchFamily
Enhanced, Energy-Efficient, Off-Line Switcher
IC With Super Peak Power Performance
Product Highlights
EcoSmart®– Extremely Energy-Efficient
• Standby output power 0.6 W for 1 W input (high line)
• Sleep mode power 2.4 W at 3 W input (high line)
• No-load consumption <200 mW at 265 VAC input
• Surpasses California Energy Commission (CEC),
ENERGY STAR, and EU requirements
PeakSwitch Features Reduce System Cost
• Delivers peak power of up to three times maximum
continuous output power
• 277 kHz operation during peak power significantly
reduces transformer size
• Programmable smart AC line sensing provides latching
shutdown during short circuit, overload and open loop
faults, and prevents glitches during power down or
brownout
• Two external components reset latch on AC removal
• Adaptive switching cycle on-time extension increases low
line peak output power, minimizing bulk capacitor size
• Adaptive current limit reduces output overload power
• Frequency jittering reduces EMI filter cost
• Tight I2f tolerances and negligible temperature variation
of key parameters ease design and lower cost
• Accurate hysteretic thermal shutdown with automatic
recovery provides complete system level overload
protection and eliminates need for manual reset
Better System Cost/Performance over RCC & Discrete
• Simple ON/OFF control – no loop compensation needed
• Very low component count – higher reliability and single
side printed circuit board
• High bandwidth provides fast turn on with no overshoot
and excellent transient load response
• Peak current limit operation rejects line frequency ripple
• Built-in current limit and hysteretic thermal protection
Applications
• Inkjet printer
• Data storage, audio amplifier, DC motor drives
Description
PeakSwitch is designed to address applications with high peak-
to-continuous power ratio demands. The very high switching
frequency during peak power loads and excellent load transient
response reduce system cost as well as component count and size.
PeakSwitch incorporates a 700 V power MOSFET, oscillator,
high voltage switched current source for startup, current limit,
AC +
IN DC
OUT
Optional Smart
AC Sense
D
PeakSwitch
S
EN/UV
BP
Figure 1. Typical Peak Power Application.
PI-3995-051006
OUTPUT POWER TABLE
230 VAC ±15%
85-265 VAC
PRODUCT3 Adapter Adapter Adapter Adapter
Cont.1 Peak2 Cont.1 Peak2
PKS603 P
13 W 32 W 9 W 25 W
PKS604 P
23 W 56 W 16 W 44 W
PKS604 Y/F 35 W 56 W 23 W 44 W
PKS605 P
31 W 60 W 21 W 44 W
PKS605 Y/F 46 W 79 W 30 W 58 W
PKS606 P
35 W 66 W 25 W 46 W
PKS606 Y/F 68 W 117 W 45 W 86 W
PKS607 Y/F 75 W 126 W 50 W 93 W
Table 1.
Notes:
1. Typical continuous power in a non-ventilated enclosed adapter
measured at +50 °C ambient.
2. Typical peak power for a period of 100 ms and a duty cycle of
10% in a non-ventilated enclosed adapter measured at +50 °C
(see Key Applications section for details).
3. See Part Ordering Information.
and thermal shutdown onto a monolithic device. In addition,
these devices incorporate auto-restart, line under-voltage sense
and frequency jittering. An innovative design minimizes audio
frequency components in the simple ON/OFF control scheme
to practically eliminate audible noise with standard varnished
transformer construction.
October 2006
Free Datasheet http://www.datasheet4u.com/




PKS604P pdf, 반도체, 판매, 대치품
PKS603-607
hysteresis of 75 °C (typical) is provided to prevent overheating
of the PC board during a continuous fault condition.
Current Limit
The current limit circuit senses the current in the power MOSFET.
When this current exceeds the internal threshold (ILIMIT), the
power MOSFET is turned off for the remainder of that cycle. The
current limit state machine reduces the current limit threshold
by discrete amounts under medium and light loads.
The leading edge blanking circuit inhibits the current limit
comparator for a short time (tLEB) after the power MOSFET is
turned on. This leading edge blanking time has been set so that
current spikes caused by capacitance and secondary-side rectifier
reverse recovery time will not cause premature termination of
the MOSFET conduction portion of the switching cycle.
During startup and fault conditions, the controller prevents
excessive drain currents by reducing the switching
frequency.
Adaptive Current Limit
When switching in the full current limit state, a skipped cycle
followed by a cycle that terminates at the full current limit
implies that the line voltage is at high line. Under this condition,
adaptive current limit reduces the full current limit level by
approximately 10% in order to reduce output overload power.
The next skipped cycle disables the adaptive current limit
condition and restores the full current limit level.
Line Under-Voltage Sense Circuit
The line under-voltage circuit prevents startup below the
programmed input voltage by connecting an external resistor
from either the DC line or from an AC sense circuit (see
Figure 1) to the EN/UV pin. The complete function is described
in the flow chart shown in Figure 5. During power up or when
the switching of the power MOSFET is disabled in auto-restart,
the current flowing into the EN/UV pin must exceed 25 µA to
initiate switching of the power MOSFET. During power up,
once the threshold is exceeded, the Bypass pin must charge from
4.8 V to 5.8 V before MOSFET switching is initiated.
The line under-voltage circuit also detects when there is no
external resistor connected to the EN/UV pin (less than ~1 µA
into pin). In this case, the line under-voltage function is disabled
and the device operates with a normal auto-restart function.
Programmable Smart AC Line Sense
When an externalAC sense circuit is used (see Figure 1), the line
under-voltage sense circuit can be used to determine the reason
for a loss of feedback signal at the EN/UV pin. In the event of
a fault condition such as output overload, output short circuit,
or an open loop condition, the power MOSFET switching is
disabled after the EN/UV pin is not pulled low for 30 ms. If the
AC line is present (IEN> 25 µA) at the time switching is disabled,

Rev. I 10/06
1. Startup
2. UV Resistor
Present?
No
Yes
No 3. AC Input
Present?
(IEN>25 µA)
Yes
4. Start Switching
9. Start Switching
No
10. No Feedback
>30 ms?
Yes
11. Stop Switching
(for 5 s)
No
5. No Feedback
>30 ms?
Yes
6. Stop Switching
Yes
7. AC Input
Present?
(IEN>25 µA)
No
8. Reset A/R Latch
Note: Normal operation
(no fault present) is denoted
by looping with a “No” response
at decision box 5 or 10.
PI-4014-062305
Figure 5. PeakSwitch Line Sense Function Flow Chart.
Free Datasheet http://www.datasheet4u.com/

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PKS604P 전자부품, 판매, 대치품
200
100
0
V
DC-INPUT
5V
BYPASS
0
Modifying current schematic
300
200
100
0
0
VDRAIN
5
Time (ms)
10
Figure 12. PeakSwitch Power Up Without Optional External UV
Resistor Connected to EN/UV Pin.
PKS603-607
200
100 VDC-INPUT
0
400
300
200 VDRAIN
100
0
0 2.5 5
Time (s)
Figure 14. Slow Power Down Timing With Optional External
(4 MW) UV Resistor Connected to EN/UV Pin.
200
100 VDC-INPUT
0
400
300
200
V
DRAIN
100
0
0 .5
Time (s)
Figure 13. Normal Power Down Timing (Without UV).
1
At maximum peak load, PeakSwitch will conduct during nearly
all of its clock cycles (Figure 7). At the rated continuous load,
it will “skip” additional cycles in order to maintain voltage
regulation at the power supply output (Figure 8). At medium
loads, cycles will be skipped and the current limit will be
reduced (Figure 9). At very light loads, the current limit will
be reduced even further (Figure 10). Only a small percentage
of cycles will occur to satisfy the internal power consumption
of the power supply at no-load.
The response time of the ON/OFF control scheme is very
fast compared to normal PWM control. This provides
tight regulation and excellent transient response.
Power Up/Down
The PeakSwitch requires only a 0.33 mF capacitor on the
BYPASS pin. Because of its small size, the time to charge this
capacitor is kept to an absolute minimum, typically less than
1.5 ms. Due to the fast nature of the ON/OFF feedback, there
is no overshoot at the power supply output. When an external
resistor is connected from the positive DC input to the EN/UV
pin, the power MOSFETswitching will be delayed during power
up until the DC line voltage exceeds the threshold (100 V).
Figures 11 and 12 show the power up timing waveform in
applications with and without an external resistor (4 MΩ)
connected to the EN/UV pin.
During power down, when an external resistor is used, the
power MOSFET will switch for 30 ms after the output loses
regulation. The power MOSFET will then remain off without
any glitches since the under-voltage function prohibits restart
when the line voltage is low.
Figure 13 illustrates a typical power-down timing waveform.
Figure 14 illustrates a very slow power-down timing waveform
as in standby applications. An external resistor is connected to
the EN/UV pin in this case to prevent unwanted restarts.
Current Limit Operation
Each switching cycle is terminated when the DRAIN current
reaches the current limit of the PeakSwitch. Current limit
operation provides good line ripple rejection.
BYPASS Pin Capacitor
The BYPASS pin uses a small 0.33 uF ceramic capacitor for
decoupling the internal power supply.

Rev. I 10/06
Free Datasheet http://www.datasheet4u.com/

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