MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MTW35N15E/D

Designer's

™ Data Sheet

TMOS E-FET .™

Power Field Effect Transistor

TO-247 with Isolated Mounting Hole

N–Channel Enhancement–Mode Silicon Gate

This advanced TMOS E–FET is designed to withstand high

energy in the avalanche and commutation modes. The new energy

efficient design also offers a drain–to–source diode with a fast

recovery time. Designed for low voltage, high speed switching

applications in power supplies, converters and PWM motor

controls, these devices are particularly well suited for bridge circuits

where diode speed and commutating safe operating areas are

critical and offer additional safety margin against unexpected

voltage transients.

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a

Discrete Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• IDSS and VDS(on) Specified at Elevated Temperature

• Isolated Mounting Hole Reduces Mounting Hardware

G

®

D

S

MTW35N15E

Motorola Preferred Device

TMOS POWER FET

35 AMPERES

150 VOLTS

RDS(on) = 0.05 OHM

CASE 340K–01, Style 1

TO–247AE

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Rating

Drain–Source Voltage

Drain–Gate Voltage (RGS = 1.0 MΩ)

Gate–Source Voltage — Continuous

Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)

Symbol

VDSS

VDGR

VGS

VGSM

Value

150

150

± 20

± 40

Unit

Vdc

Vdc

Vdc

Vpk

Drain Current — Continuous

Drain Current — Continuous @ 100°C

Drain Current — Single Pulse (tp ≤ 10 µs)

Total Power Dissipation

Derate above 25°C

ID 35 Adc

ID 26.9

IDM 105 Apk

PD 180 Watts

1.45 W/°C

Operating and Storage Temperature Range

TJ, Tstg – 55 to 150

°C

Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 80 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 Ω)

EAS 600 mJ

Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient

RθJC

RθJA

0.70 °C/W

62.5

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds

TL 260 °C

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit

curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data

1

Free Datasheet http://www.datasheet4u.com/

MTW35N15E

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled.

The lengths of various switching intervals (∆t) are deter-

mined by how fast the FET input capacitance can be charged

by current from the generator.

The published capacitance data is difficult to use for calculat-

ing rise and fall because drain–gate capacitance varies

greatly with applied voltage. Accordingly, gate charge data is

used. In most cases, a satisfactory estimate of average input

current (IG(AV)) can be made from a rudimentary analysis of

the drive circuit so that

t = Q/IG(AV)

During the rise and fall time interval when switching a resis-

tive load, VGS remains virtually constant at a level known as

the plateau voltage, VSGP. Therefore, rise and fall times may

be approximated by the following:

tr = Q2 x RG/(VGG – VGSP)

tf = Q2 x RG/VGSP

where

VGG = the gate drive voltage, which varies from zero to VGG

RG = the gate drive resistance

and Q2 and VGSP are read from the gate charge curve.

During the turn–on and turn–off delay times, gate current is

not constant. The simplest calculation uses appropriate val-

ues from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG – VGSP)]

td(off) = RG Ciss In (VGG/VGSP)

space

The capacitance (Ciss) is read from the capacitance curve at

a voltage corresponding to the off–state condition when cal-

culating td(on) and is read at a voltage corresponding to the

on–state when calculating td(off).

At high switching speeds, parasitic circuit elements com-

plicate the analysis. The inductance of the MOSFET source

lead, inside the package and in the circuit wiring which is

common to both the drain and gate current paths, produces a

voltage at the source which reduces the gate drive current.

The voltage is determined by Ldi/dt, but since di/dt is a func-

tion of drain current, the mathematical solution is complex.

The MOSFET output capacitance also complicates the

mathematics. And finally, MOSFETs have finite internal gate

resistance which effectively adds to the resistance of the

driving source, but the internal resistance is difficult to mea-

sure and, consequently, is not specified.

The resistive switching time variation versus gate resis-

tance (Figure 9) shows how typical switching performance is

affected by the parasitic circuit elements. If the parasitics

were not present, the slope of the curves would maintain a

value of unity regardless of the switching speed. The circuit

used to obtain the data is constructed to minimize common

inductance in the drain and gate circuit loops and is believed

readily achievable with board mounted components. Most

power electronic loads are inductive; the data in the figure is

taken with a resistive load, which approximates an optimally

snubbed inductive load. Power MOSFETs may be safely op-

erated into an inductive load; however, snubbing reduces

switching losses.

10000

VDS = 0 V

8000

VGS = 0 V

TJ = 25°C

6000

Crss

4000

Ciss

2000

0

10

505

VGS VDS

Coss

Crss

10 15 20

25

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4 Motorola TMOS Power MOSFET Transistor Device Data

Free Datasheet http://www.datasheet4u.com/