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PL602041 데이터시트 PDF




Micrel에서 제조한 전자 부품 PL602041은 전자 산업 및 응용 분야에서
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부품번호 PL602041 기능
기능 HCSL Frequency Synthesizer
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PL602041 데이터시트, 핀배열, 회로
PL602041
ClockWorks™ PCIe Quad Outputs
Ultra-Low Jitter, HCSL
Frequency Synthesizer
General Description
The PL602041 is a member of the ClockWorksfamily of
devices from Micrel and provides an extremely low-noise
timing solution for PCI Express clock signals.
The device operates from a 3.3V or 2.5V power supply
and synthesizes four HCSL output clocks at 25MHz,
100MHz, 125MHz, and 200MHz. The PL602041 accepts a
25MHz crystal.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Features
Input crystal frequency of 25MHz
Generates four HCSL clock outputs at 25MHz, 100MHz,
125MHz, and 200MHz
2.5V or 3.3V operating range
Typical phase jitter @ 100MHz
(1.875MHz to 20MHz): 105fs
Compliant with PCI Express Gen1, Gen2, and Gen3
Industrial temperature range (40C to +85C)
RoHS and PFOS compliant
Available in 24-pin 4mm x 4mm QFN package
Applications
Servers
Storage systems
Switches and routers
Gigabit Ethernet
Set-top boxes/DVRs
_________________________________________________________________________________________________________________________
Block Diagram
ClockWorks and Ripple Blocker are trademarks of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
January 28, 2014
Revision 1.3
[email protected] or (408) 955-1690




PL602041 pdf, 반도체, 판매, 대치품
Micrel, Inc.
Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitor, C0
Correlation Drive Level
Condition
10pF load capacitance
PL602041
Min. Typ.
Max.
Units
Fundamental, Parallel Resonant
25 MHz
50
15
pF
10 100
W
AC Electrical Characteristics(6, 7)
VDD = VDDO1/2 = 3.3V 5% or 2.5V 5%
VDD = 3.3V 5%, VDDO1/2 = 3.3V 5% or 2.5V 5%
TA = 40C to 85C. RL = 50Ω to VSS
Symbol Parameter
Condition
Min. Typ.
Max.
Units
FOUT
Output Frequency
25,
100,
125,
MHz
200
FREF
TR/TF
ODC
Crystal Input Frequency
HCSL Output Rise/Fall Time
Output Duty Cycle
20% 80%
25
150 300
48 50
450
52
MHz
ps
%
TSKEW
Output-to-Output Skew
Note 7
45 ps
TLOCK
PLL Lock Time
20 ms
TJIT()
RMS Phase Jitter(8)
100MHz
Integration Range (1.875MHz20MHz)
Integration Range (12kHz20MHz)
105
250
fs
Notes:
7. Defined as skew between outputs at the same supply voltage and with equal load conditions; measured at the output differential crossing points.
8. Measured using 25MHz crystal as the input reference source. If using an external reference input, use a low phase noise source. With an external
reference, the phase noise will follow the input source phase noise up to about 1MHz.
Truth Tables
S1
0
0
1
1
S0
0
1
0
1
OUTPUT
25MHz
100MHz
125MHz
200MHz
January 28, 2014
4 Revision 1.3
[email protected] or (408) 955-1690

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PL602041 전자부품, 판매, 대치품
Micrel, Inc.
PL602041
Figure 4. HCSL Output Load and Test Circuit
Figure 5. HCSL Recommended Application Termination (Source Terminated)
Figure 6. Crystal Input Interface
January 28, 2014
7 Revision 1.3
[email protected] or (408) 955-1690

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관련 데이터시트

부품번호상세설명 및 기능제조사
PL602041

HCSL Frequency Synthesizer

Micrel
Micrel

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