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H27UCG8T2BTR-BC PDF 데이터시트 ( Data , Function )

부품번호 H27UCG8T2BTR-BC 기능
기능 F20 64Gb MLC NAND Flash Memory
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H27UCG8T2BTR-BC 데이터시트, 핀배열, 회로
H27UCG8T2BTR-BC
64Gb(8192M x 8bit) MLC NAND Flash
F20 64Gb MLC
NAND Flash Memory
Legacy TSOP
This document is a general product description and is subject to change without notice. SK hynix does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev 0.1 / Oct. 2012
1
Free Datasheet http://www.datasheet4u.com/




H27UCG8T2BTR-BC pdf, 반도체, 판매, 대치품
H27UCG8T2BTR-BC
64Gb(8192M x 8bit) MLC NAND Flash
Table of Contents
1. Summary Description ……………………………………………………………………………………………..
1.1. Product List ……..…………………………………………………………………..………………………….….
6
6
1.2. Pin Descriptions ..…………………………………………………………………..…………………..……..... 7
1.3. Pin Diagram ............................................................................................................................... 8
1.4. Pin Assignments ………………………………………………………………………..……..…………..…….. 9
1.5. Block Diagram ............................................................................................................................ 10
1.6. Array Organization ..................................................................................................................... 10
1.7. Addressing ................................................................................................................................. 11
1.8. Extended Blocks Arrangement .................................................................................................. 11
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1.12. Bad Block Replacement …………………………………………………………………….………………….
2. Electrical Characteristics ……………………………………………………………………...…………………
15
16
2.1. Valid Blocks …………………………………………………………………………………………….………….. 16
2.2. Absolute Maximum Rating ………………………………………………………………………….…………. 16
2.3. DC and Operating Characteristics ……………………………………………………………….…………… 17
2.4. AC Test Conditions …………………………………………………………………………………….…………. 17
2.5. Pin Capacitance (TA=25, F=1.0) .......................................................................................... 18
2.6. Program/ Read / Erase Characteristics ..................................................................................... 18
2.7. AC Timing Characteristics ………………………………………………………………………….………….. 19
2.8. Status Register Coding ……………………………………………………………………………………….… 20
2.8.1. Status Register Coding For 70h/78h command ………….…………………………………….….. 20
2.8.2. Status Register Coding For 75h command ……………………….……………………………….… 21
2.9. Device Identifier Coding …………………………………………………………………………………….…. 21
2.10. Read ID Data Table ………………………………………………………………………………………….… 22
2.10.1. 3rd Byte of Device Identifier Description …………………………………………………………… 22
2.10.2. 4th Byte of Device Identifier Description …………………………………………………………… 22
2.10.3. 5th Byte of Device Identifier Description …………………………………………………………… 23
2.10.4. 6th Byte of Device Identifier Description …………………………………………………………… 23
3. Timing Diagram ………………………………………………………………………………………….………..… 24
3.1. Command Latch Cycle Timings ……………………………………………………………………….……….. 24
3.2. Address Latch Cycle Timings .………………………………………………………………………….………. 24
3.3. Input Data Latch Cycle Timings …………………………………………………………………….………… 25
3.4. Data Output Cycle Timings …………………………………………………………………………….………. 25
3.5. Data Output Cycle Timings (EDO type) ……………………………………………………………….……… 26
3.6. Read Status Cycle Timings …………………………………………………………………………….………. 26
3.7. Multi Plane Read Status Timings …………………………………………………………………….………. 27
3.8. Page Read Operation Timings .……………………………………………………………………….………. 27
3.9. Page Read Operation Timings (Intercepted by CE#) ………………………………………………….…… 28
3.10. Page Read Operation Timings with CE# don’t care …………………………………………….……… 28
3.11. Random Data Output Timings ………………………………………………………………………….……. 29
3.12. Multi Plane Page Read Operation with Random Data output Timings ……………………….…… 29
3.13. Cache Read Operation Timings ……………………………………………………………………….…….. 30
3.14. Multi Plane Cache Read Operation Timings ……………………………………………………….…….. 31
3.15. Read ID Operation Timings ……………………………………………………………………………….…. 32
3.16. Page Program Operation Timings ……………………………………………………………………….…. 32
3.17. Page Program Operation Timings with CE# don’t care ……………………………………………….. 33
Rev 0.1 / Oct. 2012
4
Free Datasheet http://www.datasheet4u.com/

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H27UCG8T2BTR-BC 전자부품, 판매, 대치품
H27UCG8T2BTR-BC
64Gb(8192M x 8bit) MLC NAND Flash
1.2. Pin Descriptions
Pin Name
I/O 0―
I/O 7
CLE
ALE
CE#
WE#
RE#
WP#
R/B#
VCCQ
VSSQ
VCC
VSS
NC
Description
DATA INPUTS/OUTPUTS
The I/O pins is used to COMMAND LATCH cycle, ADDRESS INPUT cycle, and DATA in-out
cycles during read / write operations. The I/O pins float to High-Z when the device is
deselected or the outputs are disabled.
COMMAND LATCH ENABLE
This input activates the latching of the I/O inputs inside the Command Register on the Rising
edge of Write Enable (WE#).
ADDRESS LATCH ENABLE
This input activates the latching of the I/O inputs inside the Address Register on the Rising
edge of Write Enable (WE#).
CHIP ENABLE
This input controls the selection of the device. When the device is busy, CE# low does not
deselect the memory. The device goes into Stand-by mode when CE# goes High during the
device is in Ready state. The CE# signal is ignored when device is in Busy state, and will not
enter Standby mode even if the CE# goes high.
WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The I/O inputs are latched on
the rise edge of WE#.
READ ENABLE
The RE# input is the serial data-out control, and when active drives the data onto the I/O
bus. Data is valid tREA after the falling edge of RE# which also increments the internal
column address counter by one.
WRITE PROTECT
The WP# pin, when Low, provides a hardware protection against undesired write operations.
Hardware Write Protection is activated when the Write Protect pin is low. In this condition
modify operation do not start and the content of the memory is not altered. Write Protect pin
is not latched by Write Enable to ensure the protection even during the power up phases.
READY / BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
SUPPLY VOLTAGE FOR I/O BUFFER
GROUND FOR I/O BUFFER
SUPPLY VOLTAGE
The VCC supplies the power for all the operations. (Read, Write, and Erase).
GROUND
NO CONNECTED
Table 2 : Signal descriptions
NOTE: A 0.1uF capacitor should be connected between the Vcc (Supply Voltage) pin and the Vss (Ground)
pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry
the currents required during program and erase operations.
Rev 0.1 / Oct. 2012
7
Free Datasheet http://www.datasheet4u.com/

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H27UCG8T2BTR-BC

F20 64Gb MLC NAND Flash Memory

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