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PDF H27UCG8T2BTR-BC Data sheet ( Hoja de datos )
| Número de pieza | H27UCG8T2BTR-BC | |
| Descripción | F20 64Gb MLC NAND Flash Memory | |
| Fabricantes | Hynix | |
| Logotipo |  |
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H27UCG8T2BTR-BC
64Gb(8192M x 8bit) MLC NAND Flash
F20 64Gb MLC
NAND Flash Memory
Legacy TSOP
This document is a general product description and is subject to change without notice. SK hynix does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev 0.1 / Oct. 2012
1
Free Datasheet http://www.datasheet4u.com/
1 page  
H27UCG8T2BTR-BC
64Gb(8192M x 8bit) MLC NAND Flash
3.18. Random Data Input Timings ………………………………………………………………………………… 33
3.19. Multi Plane Page Program Operation Timings ………………………………………………………….. 34
3.20.
3.21.
Copy-Back Program Operation Timings with Random Date Input .………………………………..
Cache Program Operation Timings …………………………………………………………………………
35
35
3.22. Multi Plane Cache Program Operation Timings …………………………………………………………. 36
3.23. Block Erase Operation Timings ……………………………………………………………………………… 36
3.24. Multi Plane Erase Operation Timings ...................................................................................... 37
3.25. Reset Timings …………………………………………………………………………………………………… 37
4. Device Operation …………………………………………………………………………………………………… 38
4.1. Page Read ………………………………………………………………………………………………………….. 38
4.2. Cache Read ………………………………………………………………………………………………………… 39
4.3. Cache Read Enhanced ………………………………………………………………………………………….. 39
4.4. Multi Plane Page Read ………………………………………………………………………………………….. 40
4.5. Multi Plane Cache Read ………………………………………………………………………………………... 41
4.6. Multi Plane Cache Read Enhanced ………………………………………………………………………….. 41
4.7. Read ID …………………………………………………………………………………………………………….. 42
4.8. Read Status Register ……………………………………………………………………………………………. 42
4.9. Page Program …………………………………………………………………………………………………….. 43
4.10. Multi Plane Program …………………………………………………………………………………………… 44
4.11. Cache Program .…………………………………………………………………………………………………. 45
4.12. Multi Plane Cache Program .…………………………………………………………………………………. 47
4.13. Copy-Back Program ……………………………………………………………………………………………. 48
4.14. Multi-Plane Copy-Back Program ……………………………………………………………………………. 49
4.15. Block Erase ……………………………………………………………………………………………………….. 50
4.16. Multi Plane Block Erase ……………………………………………………………………………………….. 51
4.17. Reset ………………………………………………………………………………………………………………. 51
5. Other Features ………………………………………………………………………………………………………… 52
5.1. Data Protection & Power on/off Sequence ………………………………………………………………… 52
5.2. Ready / Busy .……………………………………………………………………………………………………… 53
5.3. Write Protect Operation ………………………………………………………………………………………… 54
6. Application Notes and Comments ...…………….……………………….……………………………………… 55
6.1. Paired Page Address Information ..………………………………………………………………………….. 56
Rev 0.1 / Oct. 2012
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
H27UCG8T2BTR-BC
64Gb(8192M x 8bit) MLC NAND Flash
1.7. Addressing
Bus cycle
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
1st Cycle
2nd Cycle
3rd Cycle
A0 A1 A2 A3 A4 A5 A6 A7
A8 A9 A10 A11 A12 A13 A14 L(1)
A15 A16 A17 A17 A19 A20 A21 A22
4th Cycle
A23 A24 A25 A26 A27 A28 A29 A30
5th Cycle
A31 A32 A33
A34
L(1)
L(1)
L(1)
L(1)
Notes:
1. L must be set to Low.
2. The device ignores any additional address input cycle than required.
3. The Address consists of column address (A0~A14), page address (A15 ~ A22), plane address (A23),
and block address (A24 ~ the last address).
1.8. Extended Blocks Arrangement
The device offers 84 extended blocks to increase valid blocks. These blocks can be accessed when the block
address A34 is „High‟.
Row Address
(Hexadecimal)
0000h
0001h
0002h
0003h
0004h
0005h
07FDh
07FEh
07FFh
0800h
0801h
0852h
0853h
0853h
·
·
·
·
·
·
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
·
·
·
Block 2045
Block 2046
Block 2047
Block 2048
Block 2049
·
·
·
Block 2130
Block 2131
Main Blocks
(2048 Blocks)
Extended Blocks
(84 Blocks)
Rev 0.1 / Oct. 2012
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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