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PDF CS61305A Data sheet ( Hoja de datos )
| Número de pieza | CS61305A | |
| Descripción | T1/E1 Line Interface | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS61305A
T1/E1 Line Interface
Features
General Description
• Provides Analog Transmission Line
Interface for T1 and E1 Applications
• Provides Line Driver, Jitter Attenuator
and Clock Recovery Functions
• Transmit Side Jitter Attenuation
Starting at 3 Hz, with > 300 UI of Jitter
Tolerance
• B8ZS/HDB3/AMI Encoders/Decoders
• Compatible with SONET, M13 , CCITT
G.742, and Other Asynchronous Muxes
• 50 mA Transmitter Short-Circuit
Current Limiting
The CS61305A combines the complete analog transmit
and receive line interface for T1 or E1 applications in a
low power, 28-pin device operating from a +5V supply.
The CS61305A is a pin-compatible replacement for the
LXT305A in most applications.
The CS61305A provides a transmitter jitter attenuator
making it ideal for use in asynchronous multiplexor
systems with gapped transmit clocks. The transmitter
features internal pulse shaping and a low impedance
output stage allowing the use of external resistors for
transmitter impedance matching. The receiver uses a
digital Delay-Locked-Loop clock and data recovery cir-
cuit which is continuously calibrated from a crystal
reference to provide excellent stability and jitter toler-
ance.
Applications
• Interfacing network transmission equipment such as
SONET multiplexor and M13 to a DSX-1 cross con-
nect.
• Interfacing customer premises equipment to a CSU.
ORDERING INFORMATION
CS61305A-IP1 28 Pin Plastic DIP
CS61305A-IL1 28 Pin Plastic PLCC
[ ] = Pin Function in Extended Hardware Mode
( ) = Pin Function in Host Mode
XTALIN XTALOUT
9 10
TCLK
TPOS
[TDATA]
TNEG
[TCODE]
RCLK
RPOS
[RDATA]
RNEG
[BPV]
2
3
4 AMI,
B8ZS,
8 HDB3
CODER
7
6
LOOP
BACK
JITTER
ATTENUATOR
27 26
LLOOP RLOOP
(SCLK) (CS)
(CLKE) (INT) (SDI) (SDO)
MODE TAOS LEN0 LEN1 LEN2 TGND TV+
5 28 23 24 25
14 15
CONTROL
PULSE
SHAPER
CLOCK &
DATA
RECOVERY
13 TTIP
16
LINE DRIVER
LINE RECEIVER
19
TRING
RTIP
20 RRING
SIGNAL
QUALITY
MONITOR
1 12
21
DRIVER
MONITOR
22
17 MTIP
[RCODE]
18 MRING
[PCS]
11 DPM
[AIS]
ACLKI LOS
RV+ RGND
Preliminary Product Information This document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P. O. Box 17847, Austin, Texas, 78760
(512) 445 7222 FAX:(512) 445 7581
Copyright © Crystal Semiconductor Corporation 1996
(All Rights Reserved)
MAY ’96
DS157PP3
1
Free Datasheet http://www.datasheet4u.com/
1 page  
CS61305A
T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol Min Typ Max Units
Crystal Frequency
ACLKI Duty Cycle
ACLKI Frequency
RCLK Cycle Width
Rise Time, All Digital Outputs
Fall Time, All Digital Outputs
TCLK Frequency
TCLK Pulse Width
(Note 23)
(Note 24)
(Note 25)
(Note 26)
(Note 26)
(Notes 16, 27, 28)
(Notes 29, 30)
fc
tpwh3/tpw3
faclki
tpw1
tpwh1
tpwl1
tr
tf
ftclk
tpwh2
- 6.176000 - MHz
40 - 60 %
- 1.544 - MHz
320 648 980 ns
130 190 240 ns
100 458 850 ns
- - 85 ns
- - 85 ns
- 1.544 - MHz
80 -
- ns
150 - 500 ns
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2 25
-
- ns
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2 25 -
- ns
RPOS/RNEG Valid Before RCLK Falling
(Note 27) tsu1
150 274
- ns
RDATA Valid Before RCLK Falling
(Note 29) tsu1
150 274
- ns
RPOS/RNEG Valid Before RCLK Rising
(Note 28) tsu1
150 274
- ns
RPOS/RNEG Valid After RCLK Falling
(Note 27)
th1
150 274
- ns
RDATA Valid After RCLK Falling
(Note 29)
th1
150 274
- ns
RPOS/RNEG Valid After RCLK Rising
(Note 28)
th1
150 274
- ns
Notes: 23. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.
24. ACLKI provided by an external source or TCLK but not RCLK.
25. RCLK duty cycle will vary with extent by which pulses are displaced by jitter. Specified under worst
case jitter conditions: 0.4 UI AMI data displacement for T1 and 0.2 UI AMI data displacement for E1.
26. At max load of 1.6 mA and 50 pF.
27. Host Mode (CLKE = 1).
28. Hardware Mode, or Host Mode (CLKE = 0).
29. Extended Hardware Mode.
30. The maximum TCLK burst rate is 5 MHz and tpw2 (min) = 200ns. The maximum gap size that can
be tolerated on TCLK is 138 VI.
DS157PP3
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
CS61305A
Percent of
nominal
peak
voltage
120
110
100
90
80
269 ns
244 ns
194 ns
50
10 Nominal Pulse
0
-10
-20
219 ns
488 ns
Figure 9. Mask of the Pulse at the 2048 kbps Interface
Transmit All Ones Select
0
a) Minimum Attenuation Limit
10
AT&T 62411
20 Requirements
30
40 b) Maximum
Attenuation
50 Limit
60
Measured Performance
1 10 100 1 k 10 k
Frequency in Hz
Figure 10. Typical Jitter Attenuation Curve
Jitter Attenuator
The transmitter provides for all ones insertion at
the frequency of ACLKI. Transmit all ones is se-
lected when TAOS goes high, and causes
continuous ones to be transmitted on the line
(TTIP and TRING). In this mode, the TPOS and
TNEG (or TDATA) inputs are ignored. A TAOS
request will be ignored if remote loopback is in
effect. ACLKI jitter will be attenuated. TAOS is
not available on the CS61305A when ACLKI is
grounded.
The jitter attenuator is designed to reduce wander
and jitter in the transmit clock signal. It consists
of a 192 bit FIFO, a crystal oscillator, a set of
load capacitors for the crystal, and control logic.
The jitter attenuator exceeds the jitter attenuation
requirements of Publications 43802 and REC.
G.742. A typical jitter attenuation curve is shown
in Figure 10.
The jitter attenuator works in the following man-
ner. Data on TPOS and TNEG (or TDATA) are
For coaxial cable, For shielded twisted
75Ω l o a d a nd pair, 120Ω load and
transformer specified transformer specified
in Application Section. in Application Section.
Nominal peak voltage of a mark (pulse)
2.37 V
3V
Peak voltage of a space (no pulse)
0 ±0.237 V
0 ±0.30 V
Nominal pulse width
244 ns
Ratio of the amplitudes of positive and negative
pulses at the center of the pulse interval
0.95 to 1.05*
Ratio of the widths of positive and negative
pulses at the nominal half amplitude
0.95 to 1.05*
* When configured with a 0.47 µF nonpolarized capacitor in series with the TX transformer
primary as shown in Figures A1, A2 and A3.
Table 4. CCITT G.703 Specifications
DS157PP3
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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