PDF CS61318 Data sheet ( Hoja de datos )

Número de pieza	CS61318
Descripción	T1 Line Interface Unit
Fabricantes	Cirrus Logic
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No Preview Available ! CS61318 E1 Line Interface Unit Features Description s E1 Line Interface Unit s No Crystal Needed for Jitter Attenuation s Meets CTR-12/TBR-12 Jitter Tolerance and Attenu- ation Requirements s Meets ITU-T G.775 Requirements for LOS and AIS s Meets the BS6450 Transmitter Short-Circuit Requirements for E1 Applications s AWG for User Programmable Pulse Shapes s Line Quality Monitoring Function s TX Driver High Impedance / Low Power Control s AIS and LOS Monitoring s Generation and Detection of Loop Up / Loop Down Signaling s Selectable HDB3 Encoding/Decoding s Selectable Unipolar or Bipolar I/O s Compliant with: — ITU-T Recommendations: G.703, G.732, G.775, I.431 — ETSI ETS 300 011, 300 233, CTR 12, TBR 13 — TR-NET-00499 The CS61318 is an E1 primary rate line interface unit. This device combines the complete analog transmit and receive circuitry for a single, full-duplex interface E1 rates. The device provides jitter attenuation compliant to CTR12/TBR13 without requiring an external crystal. Al- so, the CS61318 is pin and function compatible with the Level One LXT318. In addition to a basic hardware control mode, a host mode is available that gives the user an enhanced func- tionality via a serial microprocessor interface. The extended features include custom pulse shape genera- tion, AIS and LOS monitoring functions, signal strength monitoring, and generation and detection of loop up and loop down codes. ORDERING INFORMATION CS61318-IL CS61318-IP 28-pin PLCC 28-pin PDIP TCLK TDATA/TPOS UBS/TNEG JASEL E 2N 3 C O 4 D E R 11 JITTER ATTEN REMOTE LOOPBACK LOCAL LOOPBACK (DIGITAL) RCLK RDATA/RPOS BPV/RNEG D 8E C 7O 6 D E R JITTER ATTEN TRANSMIT TIMING & CONTROL PULSE SHAPING CIRCUITRY ROM / RAM LINE DRIVERS TAOS Enable SERIAL PORT REGISTERS & CONTROL LOGIC LOS/ NLOOP Clear TIMING & DATA RECOVERY LLOOP Enable EQUALIZER CONTROL SLICERS & PEAK DETECT NOISE & CROSSTALK FILTERS LOCAL LOOPBACK (ANALOG) MAGNITUDE EQUALIZER AGC 13 TTIP 16 TRING 28 CLKE/TAOS 26 CS/RLOOP 27 SCLK/LLOOP 24 SDI/LBO1 25 SDO/LBO2 18 LATN 19 RTIP 20 RRING INT/NLOOP LOS 23 12 INBAND NLOOP & LOS PROCESSOR RECEIVE CLOCK GENERATOR 9 XTALIN 10 XTALOUT 1 MCLK 5 21 22 14 15 MODE RV+ RGND TGND TV+ Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com Copyright © Cirrus Logic, Inc. 1999 (All Rights Reserved) DS441PP2 AUG ‘99 1 Free Datasheet http://www.datasheet4u.com/ 1 page CS61318 ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0 V ±5%; GND = 0 V) Parameter Min Typ Max Transmitter AMI Output Pulse Amplitudes Transmitter Output Impedance Transformer turns ratio = 1:2 Jitter Added by the Transmitter Positive to Negative Pulse Imbalance Transmitter Short Circuit Current Receiver RTIP/RRING Input Impedance Sensitivity Below DSX (0 dB = 3.0 V) (Note 8) E1, 75 Ω (Note 9) E1, 120 Ω (Note 10) Low Z, Long Haul (Notes 11,12) 10 Hz - 8 kHz 8k Hz - 40 kHz 10 Hz - 40 kHz Broad Band (Notes 8, 12) (Notes 8, 13) Sensitivity Below G.703 (0 dB = 2.4 V) E1 - Short Haul Loss of Signal Threshold Data Decision Threshold (Note 14) Allowable Consecutive Zeros before LOS Receiver Input Jitter Tolerance - Short Haul (Note 15) 10 kHz - 100 kHz (Note 12, 15) 2 kHz (Note 12, 15) 10 Hz and below Receiver Input Jitter Tolerance - Long Haul 10 kHz - 100 kHz (Note 12, 15) 1 Hz 2.14 2.7 - - - - - - - -36 48 -15 430 - 45 160 0.35 6.0 300 0.35 138 2.37 3.0 1.5 0.015 0.015 0.015 0.020 0.2 - 20k - - - - -42 50 175 - - - - - 2.6 3.3 - - - - 0.5 50 - - - - - - 55 190 - - - - - Units V V Ω UI UI UI UI dB mA RMS Ω dB mV dB mV dB % of peak bits UI UI UI UI UI Notes: 8. Using a 0.47 µF capacitor in series with the primary of a transformer recommended in the Applications Section. 9. Pulse amplitude measured at the secondary of the transformer across a 75 Ω load. 10. Pulse amplitude measured at the secondary of the transformer across a 120 Ω load. 11. Assuming that jitter free clock is input to TCLK. 12. Not production tested. Parameters guaranteed by design and characterization. 13. Measured broadband through a 0.5 Ω resistor across the secondary of the transmitter transformer during the transmission of an all ones data pattern. 14. Data decision threshold established after the receiver equalizer filters pulse overshoot and undershoot. 15. Jitter tolerance for 0 dB input signal level. Jitter tolerance increases at lower frequencies. DS441PP2 5 Free Datasheet http://www.datasheet4u.com/ 5 Page CS61318 TRING, unless TAOS has been selected, in which case AMI-encoded continuous ones are transmitted at the TCLK frequency. The receiver RTIP and RRING inputs are ignored when local loopback is in effect. 2.8 Remote Loopback Remote loopback is selected by setting RLOOP, pin 26, high (CR1.5 = 1 in host mode). In remote loopback, the recovered clock and data input on RTIP and RRING are sent back out on the line via TTIP and TRING. Selecting remote loopback over- rides a TAOS request. The recovered clock and data from the incoming signal are also sent to RCLK, RPOS and RNEG (RDATA). Note: simultaneous se- lection of local and remote loopback modes will cause a device reset to occur (see Reset). 2.9 Network Loopback Network Loopback (automatic remote loopback) can be commanded from the network when the Network Loopback detect function is enabled. In Host Mode, Network Loopback (NLOOP) detec- tion is enabled by writing ones to TAOS, LLOOP, and RLOOP, then clearing these three bits on a suc- cessive write cycle. In hardware mode, Network Loopback can be enabled by tying RLOOP to RCLK or by setting TAOS, LLOOP, and RLOOP high for at least 200 ns, and then low. Once enabled Network Loopback functionality will remain in ef- fect until RLOOP is activated or the device is reset. When NLOOP detection is enabled, the receiver monitors the input data stream for the NLOOP data patterns (00001 = enable, 001 = disable). When an NLOOP enable data pattern is repeated for a mini- mum of five seconds (with less than 10E-3 BER), the device initiates a remote loopback. Once Net- work Loopback detection is enabled and activated by the NLOOP data pattern, the loopback is identi- cal to Remote Loopback initiated at the device. NLOOP is reset if the disable pattern (001) is re- ceived for 5 seconds, or by activation of RLOOP. NLOOP is temporarily suspended by LLOOP, but the NLOOP state is not reset. 2.10 Alarm Indication Signal The receiver sets the register bit, AIS, to “1” when less than 9 zeros are detected out of 8192 bit peri- ods. AIS returns to “0” upon the first read after the AIS condition is removed, determined by 9 or more zeros out of 8192 bit periods. 2.11 Serial Interface In the Host Mode, pins 24 through 28 serve as a mi- crocontroller interface. On-chip registers can be written to via the SDI pin or read from via the SDO pin at the clock rate determined by SCLK. Through these registers, a host controller can be used to con- trol operational characteristics and monitor device status. The serial port read/write timing is indepen- dent of the system transmit and receive timing. Data transfers are initiated by taking the chip select input, CS, low (CS must initially be high). Address and input data bits are clocked in on the rising edge of SCLK. The clock edge on which output data is stable and valid is determined by CLKE as shown in Table 1. Data transfers are terminated by setting CS high. CS may go high no sooner than 50 ns after the rising edge of the SCLK cycle corresponding to the last write bit. For a serial data read, CS may go high any time to terminate the output and set SDO to high impedance. Figure 9 shows the timing relationships for data transfers when CLKE = 0. When CLKE = 1, data bit D7 is held until the falling edge of the 16th clock cycle. When CLKE = 0, data bit D7 is held valid until the rising edge of the 17th clock cycle. SDO goes high-impedance after CS goes high or at the end of the hold period of data bit D7. SDO goes to a high impedance state when not in use. SDO and SDI may be tied together in applica- tions where the host processor has a bi-directional I/O port. DS441PP2 11 Free Datasheet http://www.datasheet4u.com/ 11 Page

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