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부품번호 | RK3188 기능 |
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기능 | Technical Reference Manual | ||
제조업체 | Rockchip | ||
로고 | |||
전체 15 페이지수
RK3188Technical Reference ManualRev 1.2
Chapter 1 Introduction
RK3188 is a low power, high performance processor for mobile phones, personal
mobile internet device and other digital multimedia applications, and integrates
quad-core Cortex-A9 with separately NEONand FPU coprocessor.
Many embedded powerful hardware engines provide optimized performance for
high-end application. RK3188 supports almost full-format video decoder by
1080p@60fps, also support H.264/MVC/VP8 encoder by 1080p@30fps,
high-quality JPEG encoder/decoder, special image preprocessor and
postprocessor.
Embedded 3D GPU makes RK3188 completely compatible with OpenGL ES2.0
and 1.1, OpenVG 1.1. Special 2D hardware engine with MMU will maximize
display performance and provide very smoothly operation.
RK3188 has high-performance external memory
interface(DDR3/LPDDR2/LVDDR3) capable of sustaining demanding memory
bandwidths, also provides a complete set of peripheral interface to support very
flexible applications as follows :
z 2 banks, 8bits/16bits Nor Flash/SRAM interface
z 4 banks, 8bits/16bits async Nand Flash,LBA Nand Flash and 8bits sync
ONFI Nand Flash, allup to 60bits hardware ECC
z Totally 2GB memory space for 2 ranks, 16bits/32bits DDR3-800,
LPDDR2-800, LVDDR3-800
z Totally 3-channels SD/MMC interface to support MMC4.41, SD3.0,
SDIO3.0 or eMMC
z Dual-channels TFT LCD interface with 4-layers , 2048x1536 maximum
display size
z One-channels, 8bits BT656 interface, 16bits BT601 DDR interface and
10bits/12bits raw data interface with image preprocessor
z Audio interface: one 2ch I2S/PCM interface and SPDIF tx interface
z One USB OTG 2.0 and one USB Host2.0 interface and HSIC interface
z 10M/100M RMII ethernet interface
z GPS interface
z High-speed ADC interface and TS stream interface
z Lots of low-speed peripheral interface : 5I2C, 4UART, 2SPI,4 PWM
This document will provide guideline on how to use RK3188 correctly and
efficiently. The chapter 1 and chapter 2 will introduce the features, block
diagram, signal descriptions and system usage of RK3188, the chapter 3
through chapter 45 will describe the full function of each module in detail.
1.1 Features
1.1.1 MicroProcessor
z Quad-core ARM Cortex-A9 MPCore processor, a high-performance,
low-power and cached application processor
z Full implementation of the ARM architecture v7-A instruction set, ARM Neon
Advanced SIMD (single instruction, multiple data) support for accelerated
media and signal processing computation
z Superscalar, variable length, out-of-order pipeline with dynamic branch
High Performance and Low-power Processor for Digital Media Application
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Free Datasheet http://www.datasheet4u.com/
RK3188Technical Reference ManualRev 1.2
Compatible with standard iNAND interface
Support MMC4.41 protocol
Provide eMMC boot sequence to receive boot data from external eMMC
device
Support combined single FIFO(32x32bits) for both transmit and receive
operations
Support FIFO over-run and under-run prevention by stopping card clock
automatically
Support CRC generation and error detection
Embedded clock frequency division control to provide programmable
baud rate
Support block size from 1 to 65535Bytes
8bits data bus width
z SD/MMC Interface
Compatible with SD3.0, MMC ver4.41
Support combined single FIFO(32x32bits) for both transmit and receive
operations
Support FIFO over-run and under-run prevention by stopping card clock
automatically
Support CRC generation and error detection
Embedded clock frequency division control to provide programmable
baud rate
Support block size from 1 to 65535Bytes
Data bus width is 4bits
1.1.5 System Component
z CRU (clock & reset unit)
Support clock gating control for individual components inside RK3188
One oscillator with 24MHz clock input and 4 embedded PLLs
Up to 2.2GHz clock output for all PLLs
Support global soft-reset control for whole SOC, also individual
soft-reset for every components
z PMU(power management unit)
6 work modes(slow mode, normal mode, idle mode, stop mode, sleep
mode, power-off mode) to save power by different frequency or
automatic clock gating control or power domain on/off control
Lots of wakeup sources in different mode
3 separate voltage domains
10 separate power domains, which can be power up/down by software
based on different application scenes
z Timer
7 on-chip 64bits Timers in SoC with interrupt-based operation
Provide two operation modes: free-running and user-defined count
Support timer work state checkable
Fixed 24MHz clock input
z PWM
Four on-chip PWMs with interrupt-based operation
Programmable 4-bit pre-scalar from apb bus clock
Embedded 32-bit timer/counter facility
Support single-run or continuous-run PWM mode
High Performance and Low-power Processor for Digital Media Application
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Free Datasheet http://www.datasheet4u.com/
4페이지 RK3188Technical Reference ManualRev 1.2
For MPEG-4,GMC(global motion compensation) not supported
For VC-1, upscaling and range mapping are supported in image
post-processor
For MPEG-4 SP/H.263/Sorenson spark, using a modified H.264 in-loop
filter to implement deblocking filter in post-processor unit
z Video Encoder
Support video encoder for H.264 ([email protected], [email protected],
[email protected]), MVC and VP8
Only support I and P slices, not B slices
Support error resilience based on constrained intra prediction and slices
Input data format :
YCbCr 4:2:0 planar
YCbCr 4:2:0 semi-planar
YCbYCr 4:2:2
CbYCrY 4:2:2 interleaved
RGB444 and BGR444
RGB555 and BGR555
RGB565 and BGR565
RGB888 and BRG888
RGB101010 and BRG101010
Image size is from 96x96 to 1920x1088(Full HD)
Maximum frame rate is up to 30fps@1920x1080Ĺ
Bit rate supported is from 10Kbps to 20Mbps
1.1.7 JPEG CODEC
z JPEG decoder
Input JPEG file : YCbCr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4
sampling formats
Output raw image : YCbCr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4
semi-planar
Decoder size is from 48x48 to 8176x8176(66.8Mpixels)
Maximum data rateĺ is up to 76million pixels per second
z JPEG encoder
Input raw image :
YCbCr 4:2:0 planar
YCbCr 4:2:0 semi-planar
YCbYCr 4:2:2
CbYCrY 4:2:2 interleaved
RGB444 and BGR444
RGB555 and BGR555
RGB565 and BGR565
RGB888 and BRG888
RGB101010 and BRG101010
Output JPEG file : JFIF file format 1.02 or Non-progressive JPEG
Encoder image size up to 8192x8192(64million pixels) from 96x32
Maximum data rateĺ up to 90million pixels per second
1.1.8 Image Enhancement
z Image pre-processor
Only used together with HD video encoder inside RK3188, not support
High Performance and Low-power Processor for Digital Media Application
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Free Datasheet http://www.datasheet4u.com/
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부품번호 | 상세설명 및 기능 | 제조사 |
RK3188 | Development board user manual | Rockchip |
RK3188 | Technical Reference Manual | Rockchip |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |