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H8S2673 데이터시트 PDF




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부품번호 H8S2673 기능
기능 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series
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H8S2673 데이터시트, 핀배열, 회로
REJ09B0283-0300
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8S/2678 Group, H8S/2678R Group,
H8S/2676 F-ZTAT
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2600 Series
H8S/2676
H8S/2675
H8S/2674R
H8S/2673
H8S/2670
HD64F2676
HD6432676
HD6432675
HD6412674R
HD6432673
HD6412670
Rev. 3.00
Revision Date: Mar 17, 2006
Free Datasheet http://www.datasheet4u.com/




H8S2673 pdf, 반도체, 판매, 대치품
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Main Revisions in This Edition
5. Contents
6. Overview
7. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
8. List of Registers
9. Electrical Characteristics
10. Appendix
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 3.00 Mar 17, 2006 page iv of l
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H8S2673 전자부품, 판매, 대치품
Main Revisions in This Edition
Item
All
Page
6.2 Input/Output Pins
Table 6.1 Pin
Configuration
124
124
7.5.1 Transfer
Modes
Table 7.4 DMAC
Transfer Modes
288
289
Section 10 I/O Ports
Table 10.1 Port
Functions
428 to
432
432
Revision (See Manual for Details)
All references to Hitachi, Hitachi, Ltd., Hitachi
Semiconductors, and other Hitachi brand names changed to
Renesas Technology Corp. Designation for categories
changed from “series” to “group”
Symbols amended
Upper column address strobe/upper data mask enable
(Before) UCAS/DQMU (After) UCAS/DQMU
Lower column address strobe/upper data mask enable
(Before) LCAS/DQML (After) LCAS/DQML
I/O description amended
Data Transfer acknowledge 0 (DMAC) (Before) DACK0
(After) Output
Table 7.4 amended
Transfer Mode
Short
address
mode
Dual address mode
(1) Sequential mode
• Memory address incremented or
decremented by 1 or 2
• Number of transfers:
1 to 65,536
(2) Idle mode
• Memory address fixed
• Number of transfers:
1 to 65,536
(3) Repeat mode
• Memory address incremented or
decremented by 1 or 2
• Continues transfer after sending
number of transfers (1 to 256) and
restoring the initial value
Transfer Source
• TPU channel 0 to 5
compare match/input
capture A interrupt
• SCI transmission complete
interrupt
• SCI reception complete
interrupt
• A/D converter conversion
end interrupt
• External request
Remarks
• Up to 4 channels can
operate independently
• External request
applies to channel B
only
• Single address mode
applies to channel B
only
Transfer Mode
Full
address
mode
Normal mode
(1) Auto-request
• Transfer request is internally held
• Number of transfers (1 to 65,536) is
continuously sent
• Burst/cycle steal transfer can be
selected
Transfer Source
Auto-request
Remarks
• Max. 2-channel
operation, combining
channels A and B
Notes amended
Modes 3*1, 7
CKE*2 DQML*2
WE*2
DQMU*2
CAS*2
RAS*2
SDRAMφ*2
Notes: 1. Mode 3 is not supported in H8S/2378 Group.
2. These pins are not supported in H8S/2678 Group.
Rev. 3.00 Mar 17, 2006 page vii of l
Free Datasheet http://www.datasheet4u.com/

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