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부품번호 AD9361 기능
기능 RF Agile Transceiver
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AD9361 데이터시트, 핀배열, 회로
Data Sheet
FEATURES
RF 2 × 2 transceiver with integrated 12-bit DACs and ADCs
Band: 70 MHz to 6.0 GHz
Supports TDD and FDD operation
Tunable channel bandwidth: <200 kHz to 56 MHz
Dual receivers: 6 differential or 12 single-ended inputs
Superior receiver sensitivity with a noise figure of 2 dB at
800 MHz local oscillator (LO)
RX gain control
Real-time monitor and control signals for manual gain
Independent automatic gain control
Dual transmitters: 4 differential outputs
Highly linear broadband transmitter
TX EVM: ≤−40 dB
TX noise: ≤−157 dBm/Hz noise floor
TX monitor: ≥66 dB dynamic range with 1 dB accuracy
Integrated fractional-N synthesizers
2.4 Hz maximum LO step size
Multichip synchronization
CMOS/LVDS digital interface
APPLICATIONS
Point to point communication systems
Femtocell/picocell/microcell base stations
General-purpose radio systems
GENERAL DESCRIPTION
The AD9361 is a high performance, highly integrated radio
frequency (RF) Agile Transceiver™ designed for use in 3G and 4G
base station applications. Its programmability and wideband
capability make it ideal for a broad range of transceiver applications.
The device combines a RF front end with a flexible mixed-signal
baseband section and integrated frequency synthesizers,
simplifying design-in by providing a configurable digital interface
to a processor. The AD9361 operates in the 70 MHz to 6.0 GHz
range, covering most licensed and unlicensed bands. Channel
bandwidths from less than 200 kHz to 56 MHz are supported.
The two independent direct conversion receivers have state-of-the-
art noise figure and linearity. Each receive (RX) subsystem includes
independent automatic gain control (AGC), dc offset correction,
quadrature correction, and digital filtering, thereby eliminating
the need for these functions in the digital baseband. The AD9361
also has flexible manual gain modes that can be externally
controlled. Two high dynamic range ADCs per channel digitize
the received I and Q signals and pass them through configurable
decimation filters and 128-tap finite impulse response (FIR) filters
to produce a 12-bit output signal at the appropriate sample rate.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
RF Agile Transceiver
AD9361
FUNCTIONAL BLOCK DIAGRAM
RX1B_P,
RX1B_N
RX1A_P,
RX1A_N
RX1C_P,
RX1C_N
RX2B_P,
RX2B_N
RX2A_P,
RX2A_N
RX2C_P,
RX2C_N
TX_MON1
TX1A_P,
TX1A_N
TX1B_P,
TX1B_N
TX_MON2
TX2A_P,
TX2A_N
TX2B_P,
TX2B_N
SPI
CTRL
AD9361
ADC
RX LO
TX LO
ADC
DAC
CTRL
DAC
GPO
PLLs
P0_[D11:D0]/
TX_[D5:D0]
P1_[D11:D0]/
RX_[D5:D0]
RADIO
SWITCHING
CLK_OUT
AUXADC AUXDACx XTALP XTALN
NOTES
1. SPI, CTRL, P0_[D11:D0]/TX_[D5:D0], P1_[D11:D0]/RX_[D5:D0],
AND RADIO SWITCHING CONTAIN MULTIPLE PINS.
Figure 1.
The transmitters use a direct conversion architecture that
achieves high modulation accuracy with ultralow noise. This
transmitter design produces a best in class TX EVM of <−40 dB,
allowing significant system margin for the external PA selection.
The on-board transmit (TX) power monitor can be used as a
power detector, enabling highly accurate TX power measurements.
The fully integrated phase-locked loops (PLLs) provide low
power fractional-N frequency synthesis for all receive and
transmit channels. Channel isolation, demanded by frequency
division duplex (FDD) systems, is integrated into the design.
All VCO and loop filter components are integrated.
The core of the AD9361 can be powered directly from a 1.3 V
regulator. The IC is controlled via a standard 4-wire serial port
and four real-time I/O control pins. Comprehensive power-down
modes are included to minimize power consumption during
normal use. The AD9361 is packaged in a 10 mm × 10 mm,
144-ball chip scale package ball grid array (CSP_BGA).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.datasheet4u.com/




AD9361 pdf, 반도체, 판매, 대치품
AD9361
Parameter1
RECEIVERS, 5.5 GHz
Noise Figure
Third-Order Input Intermodulation
Intercept Point
Second-Order Input
Intermodulation Intercept Point
Local Oscillator (LO) Leakage
Quadrature
Gain Error
Phase Error
Modulation Accuracy (EVM)
Symbol Min
NF
IIP3
IIP2
Input S11
RX1A to RX2A Isolation
RX2A to RX1A Isolation
TRANSMITTERS—GENERAL
Center Frequency
Power Control Range
Power Control Resolution
TRANSMITTERS, 800 MHz
Output S22
Maximum Output Power
Modulation Accuracy (EVM)
Third-Order Output
Intermodulation Intercept Point
Carrier Leakage
OIP3
Noise Floor
Isolation
TX1 to TX2
TX2 to TX1
TRANSMITTERS, 2.4 GHz
Output S22
Maximum Output Power
Modulation Accuracy (EVM)
Third-Order Output Intermod-
ulation Intercept Point
Carrier Leakage
OIP3
Noise Floor
Isolation
TX1 to TX2
TX2 to TX1
TRANSMITTERS, 5.5 GHz
Output S22
Maximum Output Power
Modulation Accuracy (EVM)
70
Third-Order Output
Intermodulation Intercept Point
Carrier Leakage
OIP3
Noise Floor
Isolation
TX1 to TX2
TX2 to TX1
Typ
3.8
−17
42
−95
0.2
0.2
−37
−10
52
52
90
0.25
−10
8
−40
23
−50
−32
−157
50
50
−10
7.5
−40
19
−50
−32
−156
50
50
−10
6.5
−36
17
−50
−30
−151.5
50
50
Max
6000
Rev. D | Page 4 of 36
Data Sheet
Test Conditions/
Unit Comments
dB
dBm
Maximum RX gain
Maximum RX gain
dBm Maximum RX gain
dBm At RX front-end input
%
Degrees
dB
dB
dB
dB
40 MHz reference clock
(doubled internally for
RF synthesizer)
MHz
dB
dB
dB
dBm 1 MHz tone into 50 Ω load
dB 19.2 MHz reference clock
dBm
dBc
dBc
dBm/Hz
0 dB attenuation
40 dB attenuation
90 MHz offset
dB
dB
dB
dBm 1 MHz tone into 50 Ω load
dB 40 MHz reference clock
dBm
dBc
dBc
dBm/Hz
0 dB attenuation
40 dB attenuation
90 MHz offset
dB
dB
dB
dBm 7 MHz tone into 50 Ω load
dB 40 MHz reference clock
(doubled internally for
RF synthesizer)
dBm
dBc
dBc
dBm/Hz
0 dB attenuation
40 dB attenuation
90 MHz offset
dB
dB
Free Datasheet http://www.datasheet4u.com/

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AD9361 전자부품, 판매, 대치품
Data Sheet
AD9361
Parameter1
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 2.5 V
DATA_CLK Clock Period
DATA_CLK and FB_CLK Pulse
Width
TX Data
Setup to FB_CLK
Hold to FB_CLK
DATA_CLK to Data Bus Output
Delay
DATA_CLK to RX_FRAME Delay
Pulse Width
ENABLE
TXNRX
TXNRX Setup to ENABLE
Bus Turnaround Time
Before RX
After RX
Capacitive Load
Capacitive Input
DIGITAL DATA TIMING (LVDS)
DATA_CLK Clock Period
DATA_CLK and FB_CLK Pulse
Width
TX Data
Setup to FB_CLK
Hold to FB_CLK
DATA_CLK to Data Bus Output
Delay
DATA_CLK to RX_FRAME Delay
Pulse Width
ENABLE
TXNRX
TXNRX Setup to ENABLE
Bus Turnaround Time
Before RX
After RX
Capacitive Load
Capacitive Input
SUPPLY CHARACTERISTICS
1.3 V Main Supply Voltage
VDD_INTERFACE Supply
Nominal Settings
CMOS
LVDS
VDD_INTERFACE Tolerance
VDD_GPO Supply Nominal
Setting
VDD_GPO Tolerance
Current Consumption
VDDx, Sleep Mode
VDD_GPO
Symbol Min
tCP 16.276
tMP 45% of tCP
tSTX
tHTX
tDDRX
tDDDV
1
0
0
0
tENPW
tTXNRXPW
tCP
tCP
tTXNRXSU 0
tRPRE
tRPST
2 × tCP
2 × tCP
tCP 4.069
tMP 45% of tCP
tSTX
tHTX
tDDRX
tDDDV
1
0
0.25
0.25
tENPW
tTXNRXPW
tCP
tCP
tTXNRXSU 0
tRPRE
tRPST
2 × tCP
2 × tCP
1.267
1.2
1.8
−5
1.3
−5
Typ
3
3
3
3
1.3
180
50
Max
55% of tCP
1.2
1.0
55% of tCP
1.25
1.25
1.33
2.5
2.5
+5
3.3
+5
Test Conditions/
Unit Comments
ns 61.44 MHz
ns
TX_FRAME, P0_D, and
P1_D
ns
ns
ns
ns
ns
ns FDD independent ENSM
mode
ns TDD ENSM mode
ns TDD mode
ns TDD mode
pF
pF
ns 245.76 MHz
ns
TX_FRAME and TX_D
ns
ns
ns
ns
ns
ns FDD independent ENSM
mode
ns TDD ENSM mode
ns
ns
pF
pF
V
V
V
% Tolerance is applicable
to any voltage setting
V When unused, must be
set to 1.3 V
% Tolerance is applicable
to any voltage setting
μA Sum of all input currents
μA No load
1 When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.
Rev. D | Page 7 of 36
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