PDF SG588 Data sheet ( Hoja de datos )

Número de pieza	SG588
Descripción	Low EMI Clock Generator
Fabricantes	IMI
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No Preview Available ! SG588 Approved Product Low EMI Clock Generator for Digital Camera Product Features The IMISG588 is a clock generator that integrates clock requirements for Digital Camera. It integrates a Spectrum Spread technology, a modulation technique designed specifically for reducing EMI at the fundamental frequency and its harmonics. The IMISG588 generates three output clocks: a buffered reference output (4fsc) of the crystal and 2 other clocks (CLK1,CLK2) generated by the internal Phase Lock Loops. CLK1 clock is modulated output for EMI attenuation. The IMISG588 is packaged in a 16pin TSSOP package for minimum occupation of board space. • Support clock requirements for Digital Camera • Application. • Integrates Spectrum Spread technology for • EMI attenuation. • 30 mA buffer switching current • 16 pin TSSOP package. Pin Configuration Pin Description XIN, XOUT - Forms an on-chip reference oscillator when connected to terminals of an external parallel resonant crystal, 14.318MHz for NTSC. XIN may also serve as input for an externally generated reference signal. 4fsc – Buffered reference output clock of the crystal. CLK1 and CLK2 – CLK1 and CLK2, are derived from the reference crystal oscillator by using Phase-Locked Loop (PLL). CLK1 integrates a proprietary frequency modulation technique called Spread Spectrum Clock Generation (SSCG) to reduce the Electro Magnetic Interference (EMI) found in high speed digital systems. The amount of modulation (Spread %) of CLK1 is +/- 0.5% or +/-0.1% Center-Spread. Modulation frequency of spread is 31.3995KHz. See table 1 for frequencies and function. SEL1 and SEL2 – These pins are used to select the clock frequencies, spread on/off and spread bandwidth to be modulated +/-0.5% or +/-0.1%. See table 1. These pins have internal pull-up resistors. 4fsc VDD SEL3 VSS XIN CLK2ON XOUT SEL1 1 2 3 4 5 6 7 8 16 VDD 15 VSS 14 CLK2 13 VDD 12 VSS 11 SEL2 10 SS RESET 9 CLK1 CLK2ON – This pin is used to enable/disable CLK2 output. When Low, CLK2 to be disabled, low state. When High (default), CLK2 to be enabled. This pin has an internal pull-up resistor. SS_RESET– This pin is used to reset location of SSCG profile. When signal goes high to low, the location of SSCG profile is reset to the reference frequency. This pin has an internal pull-up resistor. VDD – Circuit positive power supply. VSS – Circuit ground. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 FAX: 408-263-6571 Rev.1.4 1/12/2000 Page 1 of 7 Free Datasheet http://www.datasheet4u.com/ 1 page SG588 Approved Product Low EMI Clock Generator for Digital Camera MAXIMUM RATINGS Voltage Relative to VSS: Voltage Relative to VDD: Storage Temperature: Operating Temperature: Maximum Power Supply: -0.3V 0.3V -30ºC to + 125ºC 0ºC to + 70ºC 5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)<VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Electrical Characteristics Characteristic Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage Output High Voltage Xtal Input / Output Capacitors Supply Current Short Circuit Current Supply Voltage Range Symbol Min Typ Max Units Conditions VIL VIH IIL IIH VOL VOH CL1,2 IDD ISC VDDR - 2.0 - - - 2.4 - - - 3.0 - 0.8 -- - 100 - 100 - 0.4 -- 22 - 54 65 - 30 3.3 3.6 V V µA µA V IOL=4mA V IOH=-4mA PF X’tal’s CL=11.5pf mA mA V VDD = 3.3V, TA = 0 to 70°C and CL = 15pF Switching Characteristics Characteristic Symbol Min Typ Max Units Conditions Output Rise Time tr - 1.2 1.6 ns 0.2VDD to 0.8VDD Output Fall Time tf - 1.1 1.6 ns 0.2VDD to 0.8VDD Output Duty Cycle Tduty 45 50 55 % Vth=1.5V Absolute Jitter (CLK_1) Tj1 - 145 190 ps Vth=1.5V Absolute Jitter (CLK_2) Tj2 - 95 125 ps Vth – 1.5V Power-up Frequency Stabilization tpw-on - 50 ms From 0.9*VDD to frequency lock Conditions: VDD = 3.3V +/-10%, TA = 0 to 70°C and CL = 15pF INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 FAX: 408-263-6571 Rev.1.4 1/12/2000 Page 5 of 7 Free Datasheet http://www.datasheet4u.com/ 5 Page

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