|
|
PDF TC58NVG6T2FTA00 Data sheet ( Hoja de datos )
| Número de pieza | TC58NVG6T2FTA00 | |
| Descripción | 64 GBIT (8G X 8 BIT) CMOS NAND E2PROM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de TC58NVG6T2FTA00 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
TOSHIBA CONFIDENTIAL TC58NVG6T2FTA00
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
64 GBIT (8G 8 BIT) CMOS NAND E2PROM (Triple-Level-Cell)
DESCRIPTION
The TC58NVG6T2FTA00 is a single 3.3 V 64 Gbit (79,054,700,544 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (8192 1024) bytes 258 pages 4156 blocks.
The device has four 9216-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 9216-byte increments. The Erase operation is implemented in a single block
unit (2064 Kbytes 258 Kbytes:9216 bytes x 258 pages).
The TC58NVG6T2FTA00 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Memory cell array
Register
Page size
Block size
TC58NVG6T2FTA00
9216 1047.1171875K 8
9216 8
9216 bytes
(2064K 258K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read,
Multi Page Program, Multi Block Erase, Multi Page Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 4000 blocks
Max 4156 blocks
Power supply
VCC 2.7 V to 3.6 V
Access time
Cell array to register 110 s max
Serial Read Cycle
25 ns min
Program/Erase time
Auto Page Program
Auto Block Erase
2000 s/page typ.
3 ms/block typ.
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
50 mA max.
50mA max.
50 mA max.
100 A max
Package
TSOP I 48-P-1220-0.50C (Weight: 0.53 g typ.)
FOR RELIABILITY GUIDANCE, PLEASE REFER TO THE APPLICATION NOTES AND COMMENTS (15).
60 bit ECC for each 1K bytes is required.
1 2010-12-27C
Free Datasheet http://www.datasheet.in/
1 page  
TOSHIBA CONFIDENTIAL TC58NVG6T2FTA00
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta 0 to 70°C, VCC 2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tCLS
tCLS2
tCLH
tCS
tCS2
tCH
tWP
tALS
tALH
tDS
tDH
tWC
tWH
tWHW *
tWW
tRW
tRP
tRC
tREA
tREAID
tCR
tCLR
tAR
tRHOH
tRLOH
tRHZ
tCHZ
tCLHZ
tREH
tIR
tRHW
tWHC
tWHR
tWHRS
tR1
tR2
tR3
tWB
tRST
CLE Setup Time
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Setup Time
CE Hold Time
Write Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
WE High Hold Time from final address to first data
WP High to WE Low
Ready to WE Falling Edge
Read Pulse Width
Read Cycle Time
RE Access Time
RE Access Time for ID Read
CE Low to RE Low
CLE Low to RE Low
ALE Low to RE Low
Data Output Hold Time from RE High
Data Output Hold Time from RE Low
RE High to Output High Impedance
CE High to Output High Impedance
CLE High to Output High Impedance
RE High Hold Time
Output-High-impedance-to- RE Falling Edge
RE High to WE Low
WE High to CE Low
WE High to RE Low for data output
WE High to RE Low for Status & ID Read
Memory Cell Array to Starting Address
Data Cache Busy in Read Cache (following 31h and 3Fh)
Data Cache Busy in Read Cache (following 31h and 3Fh)
WE High to Busy
Device Reset Time (Ready/Read/Program/Erase)
0 ns
30 ns
5 ns
8 ns
20 ns
5 ns
12 ns
0 ns
5 ns
10 ns
5 ns
25 ns
10 ns
200 ns
100 ns
20 ns
12 ns
25 ns
20 ns
22 ns
10 ns
10 ns
10 ns
25 ns
5 ns
60 ns
30 ns
30 ns
10 ns
0 ns
30 ns
30 ns
400 ns
180 ns
70 s
25 s
15 s
100 ns
10/10/30/200
s
* tWHW is the time from the WE rising edge of final address cycle to the WE falling edge of first data cycle.
5 2010-12-27C
Free Datasheet http://www.datasheet.in/
5 Page 
TOSHIBA CONFIDENTIAL TC58NVG6T2FTA00
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by command operations shown
in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE , WE ,
RE and WP signals, as shown in Table 2.
Table 2. Logic Table
CLE
ALE
CE
WE
RE
WP *1
PSL*3
Command Input
HL
L
H * 0V/ VCC/ NU
Data Input
LL
L
H H 0V/ VCC/ NU
Address input
LH
L
H * 0V/ VCC/ NU
Serial Data Output
LL L H
* 0V/ VCC/ NU
During Program (Busy)
* * * * * H 0V/ VCC/ NU
During Erase (Busy)
* * * * * H 0V/ VCC/ NU
During Read (Busy)
**
**
H * * * 0V/ VCC/ NU
L
H (*2)
H (*2)
* 0V/ VCC/ NU
Program, Erase Inhibit
* * * * * L 0V/ VCC/ NU
Standby
* * H * * 0 V/VCC 0V/ VCC/ NU
H: VIH, L: VIL, *: VIH or VIL
*1: Refer to Application Note (8) toward the end of this document regarding the WP signal when Program or Erase Inhibit
*2: If CE is low during read busy, WE and RE must be held High to avoid unintended command/address input to the device or
read to device. Reset or Status Read command can be input during Read Busy.
*3: PSL must be tied to either 0V or Vcc, or left unconnected (NU).
29
2010-12-27C
Free Datasheet http://www.datasheet.in/
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet TC58NVG6T2FTA00.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| TC58NVG6T2FTA00 | 64 GBIT (8G X 8 BIT) CMOS NAND E2PROM | Toshiba |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |