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A3S12D30ETP 데이터시트 PDF




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부품번호 A3S12D30ETP 기능
기능 (A3S12D30ETP / A3S12D40ETP) 512Mb DDR SDRAM
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A3S12D30ETP 데이터시트, 핀배열, 회로
512Mb DDR SDRAM Specification
A3S12D30ETP
A3S12D40ETP
Powerchip Semiconductor Corp.
No.12 Li-Hsin Rd.1,Science-based Industrial Park ,Hsin-Chu
Taiwan, R.O.C.
TEL:886-3-5795000
FAX:886-3-5792168
Free Datasheet http://www.datasheet4u.net/




A3S12D30ETP pdf, 반도체, 판매, 대치품
Powerchip Semiconductor Corporation
A3S12D30/40ETP
512Mb DDR Synchronous DRAM
PIN FUNCTION
SYMBOL
TYPE
CLK, /CLK
Input
CKE
Input
/CS
/RAS, /CAS, /WE
Input
Input
A0-12
Input
BA0,1
Input
DESCRIPTION
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self refresh.
After self refresh mode is started, CKE becomes asynchronous input. Self refresh
is maintained as long as CKE is low.
Chip Select: When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-12. The Column Address is specified by
A0-9,11(x8) and A0-9(x16). A10 is also used to indicate precharge
option. When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
DQ0-7 (x8),
DQ0-15 (x16),
Input / Output
DQS (x8)
Input / Output
UDQS, LDQS (x16)
DM (x8)
UDM, LDM (x16)
Input
Vdd, Vss
VddQ, VssQ
Vref
Power Supply
Power Supply
Input
Data Input/Output: Data bus
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write data.
For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS
correspond to the data on DQ8-DQ15
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7;
UDM corresponds to the data on DQ8-DQ15.
Power Supply for the memory array and peripheral circuitry.
VddQ and VssQ are supplied to the Output Buffers only.
SSTL_2 reference voltage.
Free Datasheet http://www.datasheet4u.net/

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A3S12D30ETP 전자부품, 판매, 대치품
Powerchip Semiconductor Corporation
A3S12D30/40ETP
512Mb DDR Synchronous DRAM
BASIC FUNCTIONS
The A3S12D30/40ETP provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and
/WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select,
refresh option, and precharge option, respectively. To know the detailed definition of commands,
please see the command truth table.
/CLK
CLK
/CS
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
define basic commands
/WE
Command
CKE
Refresh Option @refresh command
A10 Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
precharge, READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-precharge, WRITEA)
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated
internally. After this command, the banks are precharged automatically.
Free Datasheet http://www.datasheet4u.net/

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A3S12D30ETP

(A3S12D30ETP / A3S12D40ETP) 512Mb DDR SDRAM

Powerchip
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