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PDF AN203 Data sheet ( Hoja de datos )
| Número de pieza | AN203 | |
| Descripción | Silicon-Gate Switching Functions Optimize Data Acquisition Front Ends | |
| Fabricantes | Vishay | |
| Logotipo |  |
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AN203
Vishay Siliconix
Silicon-Gate Switching Functions
Optimize Data Acquisition Front Ends
The trend in data acquisition is moving toward ever-increasing
accuracy. Twelve-bit resolution is now the norm, and sixteen
bits are not uncommon. Along with this precision, throughput
is also very important. When monitoring several hundred
channels, sample rates in the hundreds of kilohertz are not
only desirable but, in many cases, mandatory.
Analog switches and analog multiplexers find extensive use at
the heart of most data acquisition and process control
systems. This application note provides useful information
about the new high-performance DG400 family of devices. It
also reviews many design considerations that will enable you
to get the best performance in your data acquisition designs.
Silicon-Gate Technology
Vishay Siliconix’s advanced high-voltage silicon-gate CMOS
processing brings many benefits to the DG400 family of analog
switches and multiplexers: fast switching speed, low power
consumption, low charge injection, low leakage, and TTL
compatibility. In addition, this family works with reduced or
single power supplies.
The metal-gate process (Figure 1) requires that the gate
overlap with the drain and source areas to assure reliable
operation even when misalignments occur during masking
operations. This produces high gate-drain and gate-source
capacitances. The silicon-gate process, on the other hand, is
self-aligning in that it uses the silicon gate itself as a mask for
source and drain diffusions. This produces minimal overlap,
resulting in much smaller parasitic capacitances. Because the
silicon-gate process is more tightly controlled than the older
metal-gate technologies, individual devices can be spaced
closer together, resulting in smaller die that achieve equivalent
performance.
ESD Tolerance
Electrostatic discharge (ESD) has caused many CMOS
device failures, both during manufacture and during handling
or PC board assembly. Historically, CMOS devices have
shown an electrostatic discharge sensitivity (ESDS) in the
"500-V range, which was insufficient in many cases.
However, the DG400 family incorporates specially designed
ESD protection. These devices have been evaluated using the
electrostatic discharge sensitivity (ESDS) test circuit of
MIL-STD-883, Method 3015 (100-pF capacitor discharged
through a 1.5-kW resistor). The DG4XX series has a typical
overall tolerance of 1000 V. However, ESD tests on the
source/drain—with the power supply pins bypassed or
shortened—show that the DG400 through DG405 have
tolerances of more than "2000 V, whereas the DG408
through DG419 withstand > "4000 V.
S GD
ÍÍÍÍÍÍ
Oxide
pp
S GD
ÍÍÍÍÍÍÍÍÍÍPoly-Si
Oxide
pp
nn
a) Metal-Gate MOSFET
b) Silicon-Gate “Self-Aligned’ MOSFET
FIGURE 1. Comparison of Metal and Silicon-Gate Structures
Document Number: 70601
06-Aug-99
www.vishay.com S FaxBack 408-970-5600
6-1
Free Datasheet http://www.datasheet4u.net/
1 page  
AN203
Vishay Siliconix
VIN
R1
Rf1
Rf2
–
+
a)
5V
SAMPLE/HOLD
Command
VIN
S1
S2
VOUT
+
–
S1
S2
FIGURE 6. DG408 Typical Characteristics
b)
5V
VOUT
Rf1 Rf2
Rg1 Rg2
VOUT
500 mV/div
1 V/div
0 V –5 V
2 ms/div
2 ms/div
FIGURE 7. Acquisition Time Depends on Amplifier Slew Rate
The Sample-and-Hold Circuit
The sample-and-hold (S/H) circuit uses a 1/2 DG405, a fast
(tON < 250 ns) switch. In this circuit, the two switch sections are
at similar potentials in the sample mode, so when they open,
they create similar charge injections which tend to cancel each
Evaluation Results
Figure 9 shows the transfer characteristics obtained for the
three different temperature sensors used. Curve (c) is
produced by the “mV output” of a digital thermometer, using the
same thermocouple that produced curve (d). Notice the effect
that the cold-junction compensation has on the curve (i.e., it
causes a 0-V output at 0_C).
As far as resolution is concerned, all three sensors showed
satisfactory results for the 0 to 100_C range evaluated. The
thermocouple output gave a resolution equivalent to
0.05_C/bit in a 12-bit system. The RTD and AD590 outputs, as
configured, only gave the equivalent of 0.5_C/bit and 1_C/bit
resolution, respectively. However, depending on the
temperature range of interest, this circuit can be modified to
Document Number: 70601
06-Aug-99
other, therefore, helping to minimize the step error. R1 can be
trimmed to obtain the best possible charge injection
cancellation. During the hold mode, the dual switch
arrangement also helps to reduce the droop rate. Figure 7 is
a scope plot that illustrates the S/H action. Note that acquisition
time is a function of the output amplifier’s slew rate and settling
time.
produce a larger DV and offer a resolution equivalent to
0.01_C/bit.
Figure 8 shows the waveforms obtained when switching back
and forth between channel S2 (AD590) and S4 (RTD). Note
that the PGA output takes longer to settle when the AD590 is
selected. On the other hand, the lower output impedance of the
RTD sensor makes the PGA output settle about three times
faster. From these waveforms, we can estimate the throughput
of the system. Allowing 20 ms for settling times and assuming
a 12-bit A/D converter with a 15-ms conversion time,
Throughput rate = 1/35 ms = Y28 kHz
Precision will depend on the method used to read the transfer
characteristics. Factors such as ADC accuracy, transducer
accuracy, noise corruption, leakage throughout the signal
path, and amplifier offsets must be considered.
www.vishay.com S FaxBack 408-970-5600
6-5
Free Datasheet http://www.datasheet4u.net/
5 Page | ||
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