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BK1086 데이터시트 PDF




BEKEN에서 제조한 전자 부품 BK1086은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 BK1086 기능
기능 (BK1086 / BK1088) BROADCAST AM/FM/SW/LW RADIO RECEIVER
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BK1086 데이터시트, 핀배열, 회로
BK1086/88
BROADCAST AM/FM/SW/LW RADIO RECEIVER
Features
„ Worldwide 64~108 MHz FM band
support
„ Worldwide 520~1710kHz AM band
support
„ SW band support(2.3-21.85MHz,
BK1088 only)
„ LW band support(153-279kHz,BK1088
only)
„ Automatic gain control(AGC)
„ Automatic frequency control(AFC)
„ Digital FM stereo decoder
„ Automatic FM stereo/mono blend
„ Automatic noise suppression
„ 50us/75us de-emphasis
„ RDS/RBDS decoder
„ 2.4 ~ 5.5 V supply voltage
„ Wide range reference clock support
„ 32.768KHz crystal oscillator
„ 4x4 mm 24-pin QFN package
Applications
„ Table and portable radios
„ CD/DVD players
„ Modules
General Description
The BK1086/88 AM/FM receiver employs a
low-IF architecture, mixed signal image
rejection and all digital demodulation
technology. The station scan of BK1086/88
searches radio stations based on both the
channel RSSI estimation and signal quality
assessment, increases the number of receivable
stations while avoids false stops. BK1086/88
enables FM/AM/SW/LW radio reception with
low power, small board space and minimum
number of external component.
24 23 22 21 20 19
GND 1
18 VA
FMI 2
RFGND 3
GND PAD
17 GND
16 LOUT
AMI 4
BK1086/88
15 ROUT
GND 5
14 GND
NC 6
13 VD
7 8 9 10 11 12
QFN 24 Pin Assignments (Top View)
Functional Block Diagram
FM ANT
FM LNA
MIXER
RFGND
AM LNA
MIXER
PGA
PGA
ADC
ADC
RDS
DSP
DAC LOUT
DAC ROUT
32.768KHz
VDD
AUTO
TUNE
0/90
DPLL
APLL
REG BK1086/88
GPIO
SDIO
SEN
SCLK
VIO
Rev.1.0
Copyright©2010 by Beken Corporation
BK1086/88
Beken Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
Free Datasheet http://www.datasheet4u.net/




BK1086 pdf, 반도체, 판매, 대치품
2.3 Interface Bus
The BK1086/88 supports 3-wire and I2C
control interface, with up to 2.5 MHz
clock speed. User could select either of
them by setting the state of MODE pin.
BK1086/88 will use I2C interface for
MODE=0 or 3-wire interface for MODE
=1.
BK1086/88 always latches data at the
SCLK rising edge and outputs its data at
SCLK falling edge. For MCU, data
should be always written at the falling
edge of SCLK, and read out at the rising
edge of SCLK.
2.3.1 3-wire bus mode
When selecting 3-wire mode, user must
set MODE = 1. 3-wire bus mode uses
SCLK, SDIO and SEN pins. A
transaction begins when user drives SEN
Low. Next, user drives an 8-bit
command serially on SDIO, which is
captured by BK1086/88 on rising edges
of SCLK. The command consists of a 7-
bit start register address, followed by a
read/write bit (read = 1, write = 0).
BK1086/88
2.3.2 I2C bus mode
When selecting I2C mode, user must set
MODE = 0.
I2C bus mode only uses SCLK and
SDIO pins. A transaction begins with the
start condition, which occurs when
SDIO falls while SCLK is high. Next,
user drivers an 8-bit device ID serially
on SDIO, which is captured by
BK1086/88 at the rising edge of SCLK.
The device ID of BK1086/88 is 0x80.
After driving the device ID, user drives
an 8-bit control word on SDIO. The
control word consists of a 7-bit start
register address, followed by a
read/write bit (read = 1, write = 0).
For I2C host reading, the host must give
an ACK to BK1086/88 after each byte
access, and should give a NACK to
BK1086/88 after last byte read out.
For stable communication, the rising
edge time of SCLK should be less than
200ns.
0.5TCLK
Command
SDIO
Addr[6:0] + R/W
SCLK
Data[Addr]
D[15], D[14], ,
D[0]
Data[Addr+1]
D[15:0]
SEN
0.5TCLK
Figure 2. 3-Wire Interface Diagram
Data[Addr+N]
D[15:0]
0.5TCLK
0.5TCLK
Device ID
SDIO
DeviceID
SCLK
0.5TCLK
Start
ACK
Addr + R/W
Addr[6:0] + R/W
Data[Addr]
High Byte
A
C
Data[Addr]
Low Byte
K
D[15:8]
D[7:0]
Data[Addr+N]
High Byte
A
C
Data[Addr+N]
Low Byte
K
N
A
C
K
D[15:8]
D[7:0]
Figure 3. I2C Interface Diagram
0.5TCLK
Stop
Proprietary and Confidential
Page 4 of 30
Free Datasheet http://www.datasheet4u.net/

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BK1086 전자부품, 판매, 대치품
2.8 Reference Clock
The BK1086/88 accepts wide range,
from 32.768 kHz to 38.4 MHz, reference
clock input to the RCLK pin. For
frequency less than 4 MHz, it must be
multiplier of 32.768 KHz. The
BK1086/88 also support 32.768KHz
crystal oscillator. Low quality reference
clock with 200ppm is acceptable.
2.9 Initialization Sequence
To initialize BK1086/88:
1. Supply VIO.
2. Supply VA and VD. Note that VA
and VD could be supplied at the
same time of VIO supplied.
3. Provide RCLK.
4. Set the ENABLE bit high and the
DISABLE bit low to power up
BK1086/88.
To power down BK1086/88:
1. Set the ENABLE bit high and the
DISABLE bit high to place
BK1086/88 in power down mode.
Note that all register states are
maintained as long as VIO is
supplied.
2. (Optional) Remove RCLK.
BK1086/88
3. Remove VA and VD as needed.
To power up BK1086/88 (after power
down):
1. Note that VIO is still supplied in this
scenario. If VIO is not supplied,
refer to BK1086/88 initialization
procedure above.
2. Supply VA and VD.
3. Provide RCLK.
4. Set the ENABLE bit high and the
DISABLE bit low to power up
BK1086/88.
5.
VIO Supply
VA/VD Supply
RCLK Pin
ENABLE Bit
123
4
Figure 4 Initialization Sequence
Proprietary and Confidential
Page 7 of 30
Free Datasheet http://www.datasheet4u.net/

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